Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-01-04
2011-01-04
Everhart, Caridad M (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257S204000, C257SE21652, C257SE21635, C257SE29262, C257SE29189
Reexamination Certificate
active
07863174
ABSTRACT:
A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.
REFERENCES:
patent: 6034389 (2000-03-01), Burns, Jr. et al.
patent: 7521322 (2009-04-01), Tang et al.
patent: 2006/0231900 (2006-10-01), Lee et al.
patent: 10-0660881 (2006-12-01), None
patent: 10-0723527 (2007-05-01), None
Chung Hyun-Woo
Kim Hui-jung
Kim Hyun-Gi
Kim Kang-Uk
Oh Yong-chul
Everhart Caridad M
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
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