Vertical IGFET configuration having low on-resistance and method

Details Vertical IGFET configuration having low on-resistance and method Vertical IGFET configuration having low on-resistance and method

1995-02-24

1997-12-30

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257266, 257286, 257328, 257342, 437 44, 437 45, 437 51, H01L 2976, H01L 31062

Patent

active

057033897

ABSTRACT:
A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.

REFERENCES:
patent: 4532534 (1985-07-01), Ford et al.
patent: 4775879 (1988-10-01), Robb et al.
patent: 4833513 (1989-05-01), Sasaki
patent: 5208471 (1993-05-01), Mori et al.
patent: 5396097 (1995-03-01), Robb et al.
patent: 5521410 (1996-05-01), Yamamoto

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