Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-24
2001-04-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S131000, C438S132000, C438S028000, C438S467000, C438S257000, C438S529000
Reexamination Certificate
active
06218279
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a vertical fuse and method for reducing semiconductor chip layout area.
2. Description of the Related Art
Semiconductor devices such as memory devices include fuses within their structure. In dynamic random access memory (DRAM) chips, the number of fuses increases significantly for each new generation of DRAM chip designs due to increases in memory density. In conventional DRAM designs, fuses either laser blown or electrically blown, are disposed parallel to the chip direction. Fuses in this orientation will be called horizontally disposed fuses or horizontal direction fuses. Horizontally disposed fuses consume roughly 3% of the total chip area together with fuse circuitry.
One use for fuses in memory devices is to activate/deactivate areas or blocks of the chip. This may be done using anti-fuses and fuses, respectively. For example, to improve chip yield redundancies are employed which are activated by blowing fuses. For next generation DRAMs the areas for fuses will be increased significantly due to, among other things, increased redundancy. For example, if a conventional DRAM chip included 15,000 fuses, a next generation DRAM chip may include about 30,000 to about 50,000 fuses.
The present invention provides a vertically disposed fuse which may advantageously by formed without additional process and mask steps, along with metal structures of a semiconductor device. The following is a brief description of the formation of contacts/metal lines for a dual damascene process.
Referring to
FIG. 1
, a semiconductor device
10
is shown. Semiconductor device includes a substrate
12
. A dielectric layer
14
is deposited and patterned according to processes known in the art. Dielectric layer
14
may include an oxide such as TEOS or BPSG. A conductive material
16
is deposited on dielectric layer
14
. Conductive material
16
includes a metal such as tungsten or aluminum. Conductive material
16
forms metal lines or other conductive structures, for example at an M
0
level of a dynamic random access memory chip.
Referring to
FIG. 2
, a dielectric layer
18
is deposited on dielectric layer
14
and conductive layer
16
. Dielectric layer
18
is an oxide such as silicon dioxide. Dielectric layer
18
is patterned and etched to form a contact hole
20
and metal line trench
22
for a dual damascene deposition of a conductive material
24
such as aluminum as shown in
FIG. 3. A
chemical mechanical polishing (CMP) is performed to planarize a top surface and remove conductive material
24
from the surface.
Referring to
FIG. 4
, a dielectric layer
26
is deposited on dielectric layer
18
and over a contact/metal line
28
formed in dielectric layer
18
. Dielectric layer
26
is preferably an oxide such as silicon dioxide.
Referring to
FIGS. 5 and 6
, dielectric layer
26
is patterned and etched to form a via hole
32
and metal line trench
34
for a dual damascene deposition of a conductive material
36
such as aluminum to form a via/metal line
38
as shown in FIG.
6
. CMP is performed to planarize the top surface and remove conductive material
36
from the surface.
The process described in
FIGS. 1-6
is performed across semiconductor device
10
. Contact/metal line
28
and via/metal line
38
are formed within a memory array portion
30
of a memory chip, for example.
Therefore, a need exists for reducing the area occupied by fuses on a semiconductor chip. A further need exists for a method of adjusting the fuse resistance for the fuses in a semiconductor device. A still further need exists for fabricating fuses without the additional process steps and masks.
SUMMARY OF THE INVENTION
A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the liner material along vertical surfaces being melted to blow the fuse.
In alternate embodiments, the liner material preferably includes titanium nitride and the fuse preferably includes aluminum. The dielectric layer may include multiple dielectric layers. The conductive path may include a conductive line perpendicularly disposed to the fuse to form a bend between conductive line and the fuse. The current flow through the fuse may directed from the bend toward the cavity. The liner material preferably has a resistivity greater than other portions of the fuse.
A method for fabricating vertical fuses includes the steps of forming a fuse hole vertically in a dielectric layer of a semiconductor device, lining sides of the fuse hole with a conductive layer and depositing a conductive material in the fuse hole wherein the conductive layer has a resistivity greater than the conductive material, the conductive material forming a cavity having the conductive layer disposed on vertical surfaces of the cavity.
A method for fabricating vertical fuses simultaneously with contact and via structures for memory chips includes the steps of providing a memory chip including a substrate having devices formed thereon in a memory array portion of the chip, the chip further including a fuse region, depositing a first dielectric layer on the substrate, forming contacts through the first dielectric layer, depositing a second dielectric layer, simultaneously forming fuse holes and via holes, the fuse holes being formed vertically through the first and second dielectric layers, the via holes being formed down to the contacts, lining sides of the fuse holes and the via holes with a conductive layer and depositing a conductive material in the fuse holes and the via holes wherein the conductive layer has a resistivity greater than the conductive material, the conductive material deposited in the fuse holes forming a cavity in the fuse hole having the conductive layer disposed on vertical surfaces of the cavity, the fuse holes forming a larger opening than the via holes such that the same process forms cavities in the fuse holes while the via holes are filled.
In other methods, the step of depositing may include the step of depositing the conductive material using a dual damascene process. The step of depositing may include the steps of depositing a wetting layer of conductive material and depositing the conductive material in the fuse hole to form the cavity. The wetting layer is preferably deposited using a chemical vapor deposition process. The conductive material is preferably deposited using a physical vapor deposition process. The step of adjusting one of a conductive layer thickness and cavity dimensions to provide a predetermined blow voltage for the fuse may be included. The conductive material preferably includes aluminum and the conductive layer includes titanium nitride. The method may further include the step of matching a fuse resistance to a resistance in external circuitry to which the fuse is connected.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5068706 (1991-11-01), Sugia et al.
Berg Robert van den
Brintzinger Axel Christoph
Hoinkis Mark
Iggulden Roy
Narayan Chandrasekhar
Braden Stanton C.
Infineon Technologies North America Corp.
Le Dung A
Nelms David
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