Vertical channel transistor and method of fabricating the same

Details Vertical channel transistor and method of fabricating the same Vertical channel transistor and method of fabricating the same

2011-05-03

2011-05-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S173000, C438S192000, C438S206000, C438S212000, C257SE21410

Reexamination Certificate

active

07935598

ABSTRACT:
A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

REFERENCES:
patent: 5929477 (1999-07-01), McAllister Burns et al.
patent: 2007/0075359 (2007-04-01), Yoon et al.
patent: 2009/0170302 (2009-07-01), Shin et al.
patent: 1020070058906 (2007-06-01), None
patent: 10-0762907 (2007-09-01), None
patent: 10-0771871 (2007-10-01), None
English Translation of Korean Office Action for 10-2008-0112226 originally filed on Nov. 1, 2010.

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