Vertical channel masked ROM memory cell with epitaxy

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257330, 257623, H01L 2976, H01L 2994, H01L 31062, H01L 31113

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active

057478562

ABSTRACT:
A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric layer is formed on the surface of the source layer. The dielectric layer is patterned and etched forming a dielectric layer pattern with openings therein, a silicon epitaxial layer in the openings in the dielectric layer pattern. An N+ drain layer is formed on the surface of the silicon epitaxial layer. A second dielectric layer is formed on the surface of the device including the N+ drain layer. A conductor layer is formed and patterned containing silicon over the second dielectric layer. An N+ implant mask with an N+ opening over a region of the epitaxial layer is formed (source) and ion implanting through that N+ opening into the N+ implant mask in that region. A code implant mask over the conductor layer is formed and ions are implanted through the code implant mask into the device.

REFERENCES:
patent: 5244824 (1993-09-01), Sivan
patent: 5378914 (1995-01-01), Ohzu et al.
patent: 5426321 (1995-06-01), Hyodo
patent: 5637898 (1997-06-01), Baliga
IBM Technical Disclosure Bulletin vol. 32 No. 3A, pp. 77-78, Aug. 1989.
Oya, Shuichi, MOS Type Field Effect Transistor, PTO 97-2798 (Translation of Kokai 3-3478) Jun. 29, 1989.

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