Vertical channel field effect transistors having insulating...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S401000

Reexamination Certificate

active

07148541

ABSTRACT:
A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

REFERENCES:
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patent: 6242783 (2001-06-01), Ohmi et al.
patent: 6355532 (2002-03-01), Seliskar et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6885055 (2005-04-01), Lee
patent: 6998676 (2006-02-01), Kondo et al.
Fu-Liang Yang, et al., “2002 Symposium in VLSI Technology Digest of Technical Power,”IEEE, 2002.
Shengdong Zhang, et al., “Implementation and Characterization of Self-Aligned Double-Gate TFT With Thin Channel and Thick Source/Drain,”IEEE, vol. 49, No. 5, May 2002.
Yang-Kyu Choi et al., “A Spacer Patterning Technology for Nanoscale CMOS,”IEEE, vol. 49, No. 3, Mar. 2002.

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