Vertical bipolar SRAM cell, array and system, and a method...

Details Vertical bipolar SRAM cell, array and system, and a method... Vertical bipolar SRAM cell, array and system, and a method...

1999-02-12

2001-02-13

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S234000, C438S238000

Reexamination Certificate

active

06187618

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to a static random access memory (SRAM), and, more particularly, to an SRAM having a vertical bipolar pull-up transistor.
SRAM chips are well known in the art. An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. A prior art six transistor CMOS SRAM cell
1
is shown schematically in FIG.
1
. The SRAM cell
1
includes two p-type pull-up transistors
7
,
8
acting as load devices, two n-type access transistors
5
,
6
, and two n-type pull-down transistors
9
,
10
. The SRAM cell
1
has two states: logic state “0” and logic state “1”. By convention, if logic state “0” is designated by node A having a high voltage and node B having a low voltage, then logic state “1” has the opposite stored voltages, i.e. node A having a low voltage and node B having a high voltage.
In logic state “0” the high voltage on node A turns on the pull-down transistor
9
and turns off the pull-up transistor
7
, whereas the low voltage on node B turns off the pull-down transistor
10
and turns on the pull-up transistor
8
. Because the pull-down transistor
9
is on and the pull-up transistor
7
is off, current flows through the pull-down transistor
9
to a voltage supply V
SS
(ground), thereby maintaining a low voltage on node B. Because the pull-up transistor
8
is turned on and the pull-down transistor
10
is turned off, current flows from a voltage supply V
CC
through the pull-up transistor
8
, thereby maintaining a high voltage on node A.
To change the state of the SRAM cell
1
from a logic “0” to a logic “1”, a column line
3
and a column line complement
2
are provided with a low and a high voltage, respectively. Then, the access transistors
5
and
6
are turned on by a high voltage on a row line
4
, thereby providing the low voltage on the column line
3
to node A and the high voltage on the column line complement
2
to node B. Accordingly, the pull-down transistor
9
is turned off and the pull-up transistor
7
is turned on by the low voltage on node A and the pull-down transistor
10
is turned on and the pull-up transistor
8
is turned off by the high voltage on node B, thereby switching the state of the circuit from logic “0” to logic “1”. Following the switching of the state of the SRAM cell
1
, the access transistors
5
and
6
are turned off (by applying a low voltage on row line
4
). The SRAM cell
1
maintains its new logic state in a manner analogous to that described above.
However, a CMOS SRAM cell has a major disadvantage in that such a cell requires a large area on a chip surface. Each of the p-type pull-up transistors
7
,
8
require a separate n-well structure which increases the size of each SRAM cell. Further, additional processing steps are required in order to form the n-well structures.
Another prior art SRAM cell
11
is shown in
FIG. 2
, with a pair of load resistors
12
and
13
acting as the load devices. The load resistors
12
,
13
typically have a high resistance in the range of 1×10
8
to 1×10
10
ohms. The replacement of the pull-up transistors
7
,
8
with the resistors
12
,
13
decreases the size of the memory cell
11
. However, the high resistance values of the load resistors
12
,
13
increases the power consumption in the SRAM cell
11
. Although it is well known in the art to produce high resistance resistors on a small surface area by ion-implanted polysilicon to provide the desired resistance levels, there are a number of serious problems to be overcome.
For example, controlling the resistance of polysilicon during fabrication is extremely difficult. Although the load resistors
12
,
13
may be fabricated from the same layer of polysilicon used to form the polysilicon gates of the transistors
5
,
6
,
9
,
10
, typically two polysilicon layers are necessary. Specifically, one polysilicon layer is used for the load resistors
12
,
13
and V
CC
, and another polysilicon layer is used for the gates of the transistors
5
,
6
.
However, even if the SRAM cell
11
is fabricated with two polysilicon layers, the SRAM cell
11
still has several disadvantages. First, the load resistors
12
,
13
are fabricated by a complex process which produces devices having substantial variations in resistance. These variations result in low yield for such processes. Second, the load resistors
12
,
13
must provide a current which is higher than the leakage current, i.e. typically in the range of 2-10×10
−14
amps, from nodes A and B while not exceeding a level of current that creates a stand-by current problem. Providing a suitable load resistor which has high enough resistance to provide a current in this range is difficult because the load resistor must have a very high resistance, yet must occupy only a small area of the chip surface. As the density of SRAM cells in an array increases, the operating window for the resistance variation of the load resistors becomes smaller.
Another prior art SRAM cell
14
is shown in
FIG. 3
, with a pair of diodes
15
,
16
acting as the load devices. Typically, the diodes
15
,
16
are fabricated using polysilicon. However, polysilicon diodes tend to have high leakage current which increases the power consumption of the SRAM cell. Further, SRAM cells using polysilicon diodes as the load devices require three layers of polysilicon which increases the number of fabrication steps.
Another prior art SRAM cell
17
is shown in
FIG. 4
, with a pair of thin-film transistors
18
,
19
acting as the load devices. Thin-film transistors are fabricated using polysilicon and therefore suffer the same leakage current and process disadvantages of the polysilicon diodes of FIG.
3
.
Another prior art SRAM cell is disclosed in U.S. Pat. No. 5,453,636, issued to Eitan et al., in which a pair of open-base bipolar transistors are used as the load devices. The open-base bipolar transistors provide the current needed to compensate for the leakage current to the substrate or through the field effect transistors to keep the common node at the appropriate voltage level. The bipolar transistors are formed in the same p-type substrate as the other transistors of the SRAM cell. Unfortunately, such an SRAM cell suffers from the same disadvantage as the SRAM cell of
FIG. 1
in that the cell requires a large area on the chip surface since each bipolar transistor is separately formed in the substrate. Further, additional metalization steps are required to connect the collector or emitter of every bipolar transistor to the appropriate voltage source contact.
There is an ongoing need for improved SRAM cell structures which provide superior performance yet occupy a reduced area on an SRAM chip. Preferably, such improved SRAM cell structures would include a controllable pull-up device to further improve the operating characteristics of an SRAM including the cell structures.
SUMMARY OF THE INVENTION
The present invention meets this need by providing an SRAM memory cell in which a bipolar pull-up transistor is parasitically formed in the layers used to form a metal oxide semiconductor (MOS) pull-down transistor. By using a parasitic bipolar pull-up transistor, the memory cell occupies a reduced area on the SRAM chip and provides superior performance. The performance of the SRAM memory cell is further improved by controlling the conductivity of the pull-up transistor. Thus, the use of the parasitic bipolar pull-up transistor simplifies formation of the SRAM memory cell, reduces its surface area on a chip when compared to the prior art wherein such devices were formed adjacent to the SRAM memory cell and occupied additional surface area, and in addition provides improved performance.
According to a first aspect of the present invention, the SRAM memory cell is formed from a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The second semiconductor layer covers the first semiconductor layer so that the first semiconductor layer is a buri

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