Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
1999-05-08
2001-11-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S177000, C257S302000
Reexamination Certificate
active
06317357
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Complimentary metal oxide semiconductor field effect transistors (CMOS FETs) are prevalent in integrated circuit technology because they generally demand less power than bipolar transistors. Threshold voltage variations of CMOS transistors, however, are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced. In a 0.2 micron CMOS technology a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.
A basic problem with CMOS access transistors results from the fact that CMOS devices do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology. Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.
Various types of lateral MOS transistors have been described and utilized in CMOS technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an access device for use in a low voltage memory device which performs fast read access of memory data.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell access device is described which uses a combination of Bipolar and CMOS transistors.
In particular, the present invention describes a memory cell access device comprising an n-channel FET access transistor coupled between a memory cell and a data communication line, and an NPN bipolar access transistor coupled between the memory cell and the data communication line. The n-channel access transistor and the NPN bipolar access transistor are connected in parallel, and a base connection of the NPN bipolar access transistor is coupled to a body of the n-channel access transistor.
In another embodiment, a low voltage memory cell access device fabricated as a vertical pillar structure. The memory cell access device comprises an FET access transistor coupled between a memory cell and a data communication line, and a bipolar transistor coupled between the memory cell and the data communication line. The FET access transistor and the bipolar transistor are connected in parallel, with a base connection of the bipolar transistor is coupled to a body of the FET access transistor.
A memory device having a low voltage supply is also described. The memory device comprises a plurality of memory cells, a plurality of data communication bit lines, and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines. Each of the plurality of memory cell access devices comprises an FET access transistor, and a bipolar access transistor. The FET access transistor and the bipolar access transistor are connected in parallel between a memory cell and a data communication bit line.
In another embodiment, a method of accessing a memory cell is described. The method comprises the steps of activating an FET access transistor coupled between the memory cell and a data communication line for writing data charge to the memory cell, and activating a bipolar access transistor coupled between the memory cell and a data communication line for reading a charge stored on the memory cell.
REFERENCES:
patent: 3657575 (1972-04-01), Taniguchi et al.
patent: 3806741 (1974-04-01), Smith
patent: 3931617 (1976-01-01), Russell
patent: 4051354 (1977-09-01), Choate
patent: 4313106 (1982-01-01), Hsu
patent: 4604162 (1986-08-01), Sobczak
patent: 4617649 (1986-10-01), Kyomasu et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4677589 (1987-06-01), Haskell et al.
patent: 4701423 (1987-10-01), Szluk
patent: 4716314 (1987-12-01), Mulder et al.
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4888735 (1989-12-01), Lee et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4920515 (1990-04-01), Obata
patent: 4949138 (1990-08-01), Nishimura
patent: 4958318 (1990-09-01), Harari
patent: 4965651 (1990-10-01), Wagner
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5010386 (1991-04-01), Groover, III
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5083047 (1992-01-01), Horie et al.
patent: 5087581 (1992-02-01), Rodder
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5107459 (1992-04-01), Chu et al.
patent: 5110752 (1992-05-01), Lu
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5221867 (1993-06-01), Mitra et al.
patent: 5223081 (1993-06-01), Doan
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5276343 (1994-01-01), Kumagai et al.
patent: 5292676 (1994-03-01), Manning
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5329481 (1994-07-01), Seevinck et al.
patent: 5341331 (1994-08-01), Jeon
patent: 5376575 (1994-12-01), Kim et al.
patent: 5385854 (1995-01-01), Batra et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5392245 (1995-02-01), Manning
patent: 5393704 (1995-02-01), Huang et al.
patent: 5396093 (1995-03-01), Lu
patent: 5409563 (1995-04-01), Cathey
patent: 5410169 (1995-04-01), Yamamoto et al.
patent: 5414287 (1995-05-01), Hong
patent: 5416736 (1995-05-01), Kosa et al.
patent: 5422296 (1995-06-01), Lage
patent: 5422499 (1995-06-01), Manning
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432739 (1995-07-01), Pein
patent: 5438009 (1995-08-01), Yang et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5445986 (1995-08-01), Hirota
patent: 5451889 (1995-09-01), Heim et al.
patent: 5460316 (1995-10-01), Hefele
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5495441 (1996-02-01), Hong
patent: 5497017 (1996-03-01), Gonzales
patent: 5502629 (1996-03-01), Ito et al.
patent: 5504357 (1996-04-01), Kim et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508542 (1996-04-01), Geiss et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
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Mai Son
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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