Static information storage and retrieval – Systems using particular element – Capacitors
Patent
1998-02-24
1999-10-05
Mai, Son
Static information storage and retrieval
Systems using particular element
Capacitors
365177, 257302, G11C 1124
Patent
active
059634693
ABSTRACT:
A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar access transistor is described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel FET access transistor. During operation the n-channel FET access transistor is used for writing data to a memory cell, while the NPN bipolar access transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
REFERENCES:
patent: 3806741 (1974-04-01), Smith
patent: 4051354 (1977-09-01), Choate
patent: 4604162 (1986-08-01), Sobczak
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4958318 (1990-09-01), Harari
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5017504 (1991-05-01), Nishimuro et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5110752 (1992-05-01), Lu
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5223081 (1993-06-01), Doan
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5289421 (1994-02-01), Lee et al.
patent: 5292676 (1994-03-01), Manning
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5365477 (1994-11-01), Cooper, Jr. et al.
patent: 5376575 (1994-12-01), Kim et al.
patent: 5385854 (1995-01-01), Batra et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5392245 (1995-02-01), Manning
patent: 5393704 (1995-02-01), Huang et al.
patent: 5396093 (1995-03-01), Lu
patent: 5410169 (1995-04-01), Yamamoto et al.
patent: 5414287 (1995-05-01), Hong
patent: 5422499 (1995-06-01), Manning
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432739 (1995-07-01), Pein
patent: 5438009 (1995-08-01), Yang et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5445986 (1995-08-01), Hirota
patent: 5460316 (1995-10-01), Hefele
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5495441 (1996-02-01), Hong
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508542 (1996-04-01), Geiss et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
patent: 5593912 (1997-01-01), Rajeevakumar
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5644540 (1997-07-01), Manning
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5705415 (1998-01-01), Orlowski et al.
Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).
Yoshikawa, K., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996).
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 .mu.m", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Blalock T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625, (Apr. 1992).
Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 4-7, 1994).
Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).
De, V.K., et al., "Random Mosfet Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 286-287, (1997).
Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).
Sherony, M.J., et al., "Reduction of Threshold Voltage Sensitivity in SOI Mosfet's", IEEE Electron Device Letters, 16, 100-102, (Mar. 1995).
Hu, G., et al., "Evening Panel Discussion--Will Flash Memory Replace Hard Disk Drive", IEDM Technical Digest, (Dec. 11, 1994).
Sun, J., "CMOS Technology for 1.8C and Beyond", Int'l Symp on VLSI Technology, Systems and Applications: Digest of Technical Papers, 293-297, (1997).
Takao, Y., et al., "A 4-um Full-CMOS SRAm Cell Technology for 0.2-um high Performance Logic LSIs", 1997 Symp. on VLSI Technology: Digest of Technical Papers, Kyoto, JP, 11-12, (1997).
Alder, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM Journal of Research and Development, 39, 167-188, (Jan./Mar., 1995).
Askin, H.O., et al., "Fet Device Parameters Compensation Circuit", IBM Technical Disclosure Bulletin, 14, 2088-2089, (Dec. 1971).
Banerjee, S.K., et al., "Characterization of Trench Transistors for 3-D Memories", 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, 79-80, (May 28-30, 1986).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).
Chen, M.J., et al., "Optimizing the Match in Weakly Inverted Mosfet's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30-Oct. 3, 1996).
Clemen, R., et al., "VT-compensated TTL-Compatible Mos Amplifier", IBM Technical Disclosure Bulletin, 21, 2874-2875, (1978).
DeBar, D.E., "Dynamic Substrate Bias to Achieve Radiation Hardening", IBM Technical Disclosure Bulletin, 25, 5829-5830, (1983).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-Mosfet's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Fong, Y., et al., "Oxides Grown on Textured Single-Crystal Silicon--Dependence on Process and Application in EEPROMs", IEEE Transactions on Electron Devices, 37, 583-590, (Mar. 1990).
Forbes, L., "Automatic On-chip Threshold Voltage Compensation", IBM Technical Disclosure Bulletin, 14, 2894-2895, (1972).
Frantz, H., et al., "Mosfet Substrate Bias-Voltage Generator", IBM Technical Disclosure Bulletin, 11, 1219-1220, (Mar. 1969).
Gong, S., et al., "Techniques for Reducing Switching Noise in High S
Mai Son
Micro)n Technology, Inc.
LandOfFree
Vertical bipolar read access for low voltage memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical bipolar read access for low voltage memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical bipolar read access for low voltage memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1179313