Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2002-06-18
2004-10-12
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
Reexamination Certificate
active
06803295
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to the fabrication and operation of semiconductor devices and, more particularly, to apparatus and methods for limiting the diffusive ingress of mobile charges into silicon on insulator (SOI) semiconductor structures during fabrication and operation of a semiconductor device.
BACKGROUND OF THE INVENTION
The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every sub-structure within a semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of semiconductor devices have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also magnified the importance of semiconductor material properties and behaviors.
In the past, most semiconductor devices were fabricated directly on a bulk silicon substrate. Recently, however, semiconductor manufacturers have started to fabricate semiconductor devices on substrates having varied compositions. One such variety of substrate that is gaining in acceptance and popularity is silicon on insulator (SOI). The insulator configuration of SOI substrates offers semiconductor device designers a number of performance improvements over plain silicon substrates, such as improved leakage currents and improved latch-up characteristics. SOI substrates typically comprise a relatively thin silicon layer disposed atop an insulator layer, which is typically an oxide and which is, in turn, disposed atop a relatively thick bulk silicon layer. SOI substrates are manufactured in a variety of ways. One such method comprises sandwiching an oxide between two bulk silicon substrates, and then grinding the upper bulk silicon substrate down until only a thin silicon layer remains. Regardless of the method used to produce an SOI substrate, most semiconductor fabrication processes do not encompass the actual production of the SOI wafer. Most semiconductor fabrication processes comprehend the use of a finished SOI substrate. Device fabrication then begins on top of the thin silicon layer.
The transition to SOI substrates has not been completely problem free. Because of their heterogeneous composition, SOI substrates are susceptible to a number of problems not encountered with bulk silicon substrates. One major problem facing SOI substrates, and semiconductor devices utilizing SOI substrates, is mobile ion migration. There are numerous sources (e.g., humans, chemicals) of potentially detrimental mobile charge present in every fabrication process. The semiconductor industry has identified certain ions (e.g., sodium), as particularly detrimental, since semiconductor devices are sensitive to charge. The core functionality of semiconductor devices rests on the ability to control charges, and charge migration, within a device structure. Thus, the presence of random mobile charges within a device structure causes a number of performance and reliability problems.
A mobile charge's mobility differs, depending on the material it travels in. Mobile charges like sodium have a high degree of mobility in oxides, especially those typically found in SOI substrates (e.g., silicon dioxide). SOI technologies are particularly concerning since an exposed insulator layer provides a highly susceptible path for transient mobile charges to migrate towards device structures. Typically, this insulator comprises a buried oxide layer, running contiguously throughout the substrate. The insulator layer may be exposed to mobile charge after a base SOI substrate (or wafer) is produced, and is almost always exposed after individual devices (or die) are cleaved from the wafer. It is therefore important to provide barriers to mobile charge around a silicon chip so that mobile charges do not reach active circuitry and devices.
Semiconductor producers have thus far addressed this problem through the use of a scribe seal. For each individual die on a wafer, a scribe line is drawn—demarcating where the die will actually be cut from the wafer. The scribe seal concept provides a buffer structure disposed around the perimeter of each individual die as close to the scribe line as possible—sealing off the circuitry disposed upon the die within the scribe seal from mobile charge ingress at the cut edge of the die. Within conventional SOI-based semiconductor devices, the scribe seal usually comprises structure formed beneath the surface of the SOI substrate, upon which other structures are formed in the device levels (e.g., using contiguous structures in levels Metal 1, Via 1, Metal 2, etc.). These scribe seal structures typically utilize and rely upon materials that are resistant to, or completely impede, the diffusive migration of mobile charges, such and metals and certain nitrides.
Most conventional scribe seals are formed in a multi-step process. In order to extend the scribe seal below the surface of an SOI substrate, and down through the insulator layer, conventional processes typically rely on an etch-and-fill methodology. Such a process is depicted in
FIGS. 1
a
through
1
c
.
FIG. 1
a
depicts an SOI substrate
100
, comprising a bulk silicon layer
102
, an insulator layer
104
, and an upper silicon layer
106
. A mask layer
108
is selectively deposited upon wafer
100
, such that an aperture is formed in the mask layer where the scribe seal is desired. An etching process is then applied to wafer
100
, which may comprise a gross etch (i.e., any material) or a multi-step selective etch (e.g., Si selective etch, followed by oxide selective etch, followed by Si selective etch). After the etching processes have formed a sufficient trench
110
in wafer
100
, mask
108
is removed from wafer
100
, as depicted in
FIG. 1
b
. Trench
110
is then filled with an appropriate material (e.g., metal) to form barrier
112
, as depicted in
FIG. 1
c
. Barrier
112
inhibits the diffusive migration of free mobile charges
114
into wafer
100
through insulator layer
104
. As a semiconductor device is fabricated on the upper surface
116
of wafer
100
, other scribe seal structures can be formed upon and coupled to barrier
112
to fully encapsulate an active semiconductor device region.
Although such conventional approaches are arguably effective at inhibiting the migration of mobile ions, they are also fraught with a number of limitations and problems. Methodologies, such as those described above, require significant additional processing steps during device fabrication. Formation of an adequate barrier for most SOI substrates requires formation and filling of a relatively deep, contiguous trench around the perimeter of the die. This complicates the device fabrication process, and increases device cost and production time. Furthermore, mechanical characteristics of such structures raise a number of reliability issues. These conventional barrier structures are prone to long-term stability and integrity problems—often due to extreme aspect ratios resulting from relatively tall structures of extremely narrow width, and from the excavation and filling of a relatively large trench in the substrate. For example, metal-based scribe seals may tear or peel, leaving a breach in the seal through which mobile charges can migrate and affect device performance. Finally, conventional methods' heavy reliance on metallization as a barrier limits the processes available for, and applications of, mobile charge barriers.
SUMMARY OF THE INVENTION
Therefore, a versatile system for limiting the diffusive ingress of mobile ions into SOI semiconductor structures during fabrication and operation of a semiconductor device is now needed, providing for efficient, reliable, and cost-effective semiconductor device buffering while overcoming the aforementioned limitations of conventional methods.
The present invention recognizes
Hollingsworth Deems Randy
Rost Timothy A.
Brady III Wade James
Dolan Jennifer M.
Jr. Carl Whitehead
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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