Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-09-24
2004-05-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S542000, C438S683000, C438S778000, C438S798000, C427S452000
Reexamination Certificate
active
06730616
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, in general, to improving electrical connections in semiconductor device processing and, in particular, to improving electrical connections to materials with high dielectric constants, such as in the construction of capacitors.
BACKGROUND OF THE INVENTION
The increasing density of high performance integrated circuits (e.g., Gbit range DRAMs) is increasing the need for the use of materials with high dielectric constants in electrical devices and structures, such as capacitors. Generally, capacitance is directly related to the surface area of an electrode in contact with the capacitor dielectric, but is not significantly affected by the electrode volume. Current methods generally utilized to achieve higher capacitance per unit area increase the surface area/unit area by increasing the topography, such as in trench and stack capacitors using SiO
2
or SiO
2
/Si
3
N
4
as the dielectric. This approach becomes very difficult in terms of manufacturability for devices such as high capacity DRAM.
An alternative approach is to use a high permittivity dielectric material. Many perovskite, ferroelectric, or high dielectric constant (hereafter abbreviated HDC) materials, such as (Ba,Sr)TiO
3
(BST), usually have much larger capacitance densities than standard SiO
2
—Si
3
N
4
—SiO
2
capacitors. Various metals and metallic compounds, and typically noble metals such as Pt and conductive oxides such as RuO
2
, have been proposed as the electrodes for these HDC materials. To be useful in electronic devices, however, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of these high dielectric constant materials.
As used herein, the term “high dielectric constant” means a dielectric constant of about 50 or greater at device operating temperature. HDC materials are useful for the fabrication of many electrical devices, such as capacitors. However, HDC materials are generally not chemically stable when deposited directly on a semiconductor substrate, so one or more additional layers are required to provide the electrical connection between the HDC material and the substrate. The additional layer or layers should generally be chemically stable when in contact with the substrate and also when in contact with the HDC material. Additionally, due to unit area constraints, high-density devices (e.g., Gbit range DRAMs) generally require a structure in which the lower electrode is conductive from an HDC material down to a substrate.
The deposition of an HDC material usually occurs at a high temperature (generally greater than about 500° C.) in an oxygen-containing atmosphere. An initial electrode structure formed prior to this deposition should be stable both during and after this deposition, while subsequent electrode structures formed after this deposition need only be stable after this deposition.
As already noted, ferroelectrics such as BST are promising high-density dielectrics, and they have achieved much larger capacitance densities than SiO
2
—Si
3
N
4
—SiO
2
(ONO) capacitors. These dielectrics require metallic top and bottom electrodes. The bottom electrode in particular must be stable during the deposition of oxide, which occurs at high temperature (greater than 500° C.) in an oxygen-containing atmosphere. Therefore, two types of materials have been evaluated as the lower electrode, a noble metal, such as Pt, or a conductive oxide, such as RuO
2
. There are, however, a number of problems with electrodes formed of these materials. Many of these problems are related to choice of materials, processing, and integration.
Some of these issues are better understood in light the following examples of conventional device structure illustrated in
FIGS. 1
,
2
A and
2
B.
FIG. 1
depicts a device geometry
100
that is relatively simple in terms of demands on the electrode. In this geometry, contact is made through bottom electrode
102
, and buffer layer
104
is needed only as a sticking layer. In contrast, geometries
200
and
202
, of
FIGS. 2A and 2B
, respectively, require electrical contact through both bottom electrode
204
and buffer layer
206
to the substrate
208
. In
FIG. 2A
, contact is made directly to substrate
208
. In contrast,
FIG. 2B
utilizes a plug
210
. The electrode structure of geometries
200
and
202
retains its conductivity even after the deposition of a dielectric, if an appropriate barrier layer(s) is used between the conductive oxide and the silicon substrate.
As previously noted, the lower electrode in contact with the high dielectric constant materials is typically either a noble metal, such as Pt, or a conductive oxide, such as RuO
2
. Pt has several problems, when used as a lower electrode, which prevent it from being used alone. Pt usually allows oxygen to defuse through it and, hence, allows neighboring materials to oxidize. Pt does not stick very well to traditional dielectrics, such as SiO
2
or Si
3
N
4
. Pt rapidly forms a silicide at low temperatures, and readily forms hillocks under stress.
Currently, electrodes most commonly used for BST are Pt (as electrode
204
) and Ta (as buffer
206
), and TiN for a top electrode
212
. During BST deposition, Ta oxidizes and becomes an insulating material. Such a process produces an electrode that is suitable for geometry
100
of
FIG. 1
, but not for geometries
200
or
202
. Other electrode structures have been proposed, including alloys of Pt, Pd, and Rh (as electrode
204
), and oxides made of Re, Os, Rh, and Ir (as buffer
206
), on Si or polysilicon. Another structure that has been proposed uses Pt as bottom electrode
204
, with TiN/Ti as buffer layer
206
. This structure is believed to be stable below 600° C. Degradation is dependant on the thickness, deposition technique of the TiN, TiSi
2
and Pt layers.
Thus, most conventional attempts to create a more stable bottom electrode for high dielectric constant materials focus on changing a diffusion barrier material into something more stable to oxygen. This often results is extremely complex and expensive device processing methods, capable of introducing a number of flaws into the resulting products. Furthermore, most conventional processes and methodologies do not provide for selective deposition of diffusion barrier material, and thus selective oxidation.
SUMMARY OF THE INVENTION
Therefore, a versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, allows for selective deposition and selective oxidation, utilizing existing production compounds and materials, while resulting in uniform and proper device structuring, is now needed; providing cost-effective and efficient processing and device performance while overcoming the aforementioned limitations of conventional methods.
The present invention provides a system, simplifying device processing by using a reactive plasma to form diffusion barriers. The present invention may be applied utilizing any number of conventional device fabrication materials, thus providing an economical solution to complex device manufacturing. The present invention provides the ability to selectively form diffusion barriers, only where desired, and thus provides for selective oxidation.
More specifically, the present invention provides a method of preparing a semiconductor device for selective oxidation. A first device structure is formed. A selected portion of the first device structure is then chemically altered, using any one of a number of fabrication processes. An oxide is then disposed upon the chemically altered portion of the first device structure.
The present invention also provides a method of forming a diffusion barrier within a semiconductor device. A first device structure provided. A selected portion of the first device structure is then nitrided. A second device structure is then disposed upon the nitrided portion of the first device structure.
REFERENCES:
patent: 6277448 (2001-08-01), Strutt et al.
patent: 6346465 (2002-02-01), Miura et al.
patent: 64
Berry Renee R.
Brady W. James
Hoel Carlton H.
Nelms David
Telecky , Jr. Frederick J.
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