Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-22
2008-07-22
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000
Reexamination Certificate
active
11200614
ABSTRACT:
A method of verifying event handling for a device under test comprised of hardware description language logic within a verification environment can include, for each trigger specified by the verification environment, creating an associated thread within the verification environment. The method also can include defining a time span during which event handling within a device under test is to be performed responsive to each trigger and determining whether event handling for each trigger is performed within the time span associated with that trigger. Event handling for each trigger can be monitored by the thread associated with that trigger. The method further can include indicating triggers that were not handled by the device under test.
REFERENCES:
patent: 5905883 (1999-05-01), Kasuya
patent: 7234093 (2007-06-01), Kadkade
patent: 7234094 (2007-06-01), Kadkade et al.
Cuenot Kevin
Tu Christine T
Xilinx , Inc.
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