Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2003-07-22
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S015000, C714S724000, C714S731000, C714S741000, C714S744000
Reexamination Certificate
active
06598191
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to digital systems, and, more particularly to an apparatus and method for verifying the asynchronous boundary behavior of a digital system, such as a computer system, where the asynchronous boundary is formed between two or more clock domains in the digital system.
BACKGROUND OF THE INVENTION
Today's digital systems, such as computer systems, often incorporate multiple clock domains within their designs. When multiple clock domains exist within a digital system, asynchronous boundaries are formed between adjacent clock domains. Signals crossing an asynchronous boundary from a write clock domain to a read clock domain are typically synchronized through a series of registers (e.g., flip-flops) in the read clock domain before being used. This is done to avoid a condition known as metastability.
Metastability occurs if the clock in the read domain transitions at approximately the same time as the input signal from the write domain transitions. As an example, the read domain may read one or more input signals from the write domain that are at an indeterminate voltage level which is neither a logical “0” voltage level nor a logical “1” voltage level. The synchronizing flip-flops in the read domain bring the input signals to a consistent logical “0” or logical “1” state before the signals are used in the read domain. However, the outputs generated by the synchronizing flip-flops now become non-deterministic (i.e., either a logical “0” or a logical “1”) when there is a change in the input signals at approximately the same time that the clock for the read domain is transitioning (i.e., rising edge for positive edge triggered flip-flops or falling edge for negative edge triggered flip-flops).
In addition to metastability arising from asynchronous read domain and write domain clocks, signals crossing asynchronous boundaries between clock domains can have differing delays due to varying RC and loading delays, which further contributes to the metastability problem. Also, clock skew between the various synchronizing flip-flops may produce non-deterministic results at the outputs of the flip-flops.
Thus, if input signals from the write domain are transitioning just before the triggering edge of the read clock, the situation can occur where some of the input signals complete transitioning before the synchronizing flip-flop is triggered, while other input signals do not complete transitioning before the synchronizing flip-flop is triggered, due to high RC delays and/or clock skew. As a result, the latest values of some input signals from the write domain are propagated to the read domain, while old values of other input signals are propagated.
Verification of digital systems having asynchronous boundaries as a result of multiple clock domains poses serious problems for existing verification tools. A simulator for simulating a digital system which is typically written in a hardware description language (HDL), such as Verilog or VHDL cannot effectively model signal transitions at asynchronous boundaries. The simulations controlled by the simulators are digital in nature with a strict notion of events (e.g., signal transitions) happening only at precise time intervals. However, because of conditions described above (i.e., RC delays and/or clock skew) signal transitions do not occur at the precise time intervals utilized by the simulators. Thus, simulators fail to capture the uncertainty inherent in digital systems having asynchronous boundaries. Rather than capturing the actual behavior (i.e., some signals have transitioned to the new state, while other signals have not yet transitioned to a new state), the simulators assign either the pre-transition state to all of the signals, or the post-transition state to all of the signals.
Most simulators allow delay behavior to be modeled to delay the transition by a predetermined amount of time. Nevertheless, the delay signals modeled are still deterministic since at the end of the predetermined delay period, the signals transition instantly.
A hardware emulator is a software module whose behavior matches the corresponding digital system, but whose implementation is simpler than a hardware model. A hardware emulator can be written in any number of programming languages, such as C, C++, and PASCAL, and can be written in a hardware description language, such as Verilog and VHDL; Unlike hardware models, hardware emulators do not suffer from constraints of the physical implementation, such as silicon area. Hardware emulators also have no obligation to meet any physical constraints. Hardware emulators are capable of modeling some of the uncertainty associated with metastability. However, the uncertainty imposed due to RC delays and clock skews cannot be modeled accurately, since the actual values depend on the final layout of the chip and other fabrication parameters.
In view of the above, there is a need for an apparatus and a method to verify the asynchronous boundary behavior of a digital system, where the asynchronous boundary is formed between two or more clock domains in the digital system. The apparatus and method preferably captures and propagates any signal uncertainty present at the asynchronous boundary. The apparatus and method preferably operates correctly in digital systems where the two or more clock domains operate on the same frequency or different frequencies. Finally, the apparatus and method preferably is capable of operating within all clock domains of the digital system.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for verifying the functional behavior of a digital system. The digital system includes a first series of interconnected registers clocked by a first clock and a second series of interconnected registers clocked by a second clock. An asynchronous boundary is formed at a coupling between the first series of interconnected registers and the second series of interconnected registers. The apparatus includes a delay register, which is coupled to an output of a predetermined register. The predetermined register is predetermined from a group of registers including the last register of the first group of interconnected registers and all registers from the second group of interconnected registers. The delay register is clocked by the same clock as the predetermined register. The apparatus also includes a multiplexer. The multiplexer includes at least two multiplexer inputs coupled to the output of the predetermined register and an output of the delay register. The multiplexer also includes a multiplexer output coupled to an input of a next register in the second series of interconnected registers. Finally, the multiplexer includes a multiplexer input selector, and a selector coupled to the multiplexer input selector for selecting which of the at least two multiplexer inputs to pass through to the multiplexer output.
In one embodiment of the present invention, the selector is a pseudo-random signal generator. In one embodiment, the pseudo-random signal generator is disabled if a triggering edge of the first clock occurs at least a predetermined time interval from the triggering edge of the second clock. The first clock and the second clock operate at approximately the same frequency.
The present invention also provides an apparatus for verifying an asynchronous boundary behavior of a digital system, the digital system including a first register clocked by a first clock, and a second register clocked by a second clock. The apparatus includes a delay register coupled to an output of the first register, wherein the delay register is clocked by the first clock. The apparatus further includes a multiplexer. The multiplexer includes at least two multiplexer inputs, the first multiplexer input coupled to the output of the first register and the second multiplexer input coupled to an output of the delay register. The multiplexer also includes a multiplexer output coupled to an input of the second register. Finally, the multiplexer includes a multiple
Das Sharma Debendra
Gupta Ashish
Williamson Donald A.
Dildine R. Stephen
Hewlett-Packard Development Companay, L.P.
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