VDMOS transistor protected against over-voltages between...

Details VDMOS transistor protected against over-voltages between... VDMOS transistor protected against over-voltages between...

2001-01-09

2002-03-26

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S208000, C438S268000

Reexamination Certificate

active

06362036

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and, more particularly, to a VDMOS transistor in an integrated circuit.
BACKGROUND OF THE INVENTION
In some circuit applications for vertical double-diffusion MOS (VDMOS) transistors, the voltage between the gate and source electrodes may reach values very close to the breakdown voltage of the gate dielectric. This may cause degradation of the dielectric, or may even reach the breakdown value of the gate dielectric so that the transistor becomes unusable.
A known circuit which uses a VDMOS transistor is shown schematically in FIG.
1
. It is a current generator comprising an npn bipolar transistor, indicated T
1
, and an n-channel VDMOS transistor, indicated T
2
, connected to the npn transistor in a “cascode” arrangement. The emitter of the npn transistor is connected to a supply terminal, indicated by the ground symbol. The drain terminal of the VDMOS transistor is connected, via a load RL, to a second supply terminal, indicated VDD. A predetermined voltage VR is applied to the base of the npn transistor and the gate terminal of the VDMOS transistor is connected to a reference-voltage generator represented by a Zener diode DZ in series with a constant-current generator G.
Between the collector of the npn transistor T
1
and the ground terminal there is a parasitic diode D
1
which represents the reverse-biased junction between the n-type collector region and the integrated circuit p-type substrate, which is connected to the ground terminal as is the emitter of the transistor. Between the drain and source terminals of the VDMOS transistor T
2
there is a further parasitic diode D
2
which represents the reverse-biased junction between the body region of the transistor, which is in contact with the source electrode, and the drain region of the transistor.
The circuit described above can supply to the load RL a current having a value which depends upon the supply voltage VDD, upon the voltage VR, and upon the reverse-conduction threshold of the Zener diode DZ. A particularly critical operating condition arises when the transistor T
1
is cut off. In this situation, the generator current results solely from the leakage currents of the two diodes D
1
and D
2
. A voltage which depends upon the supply voltage VDD and upon the equivalent resistances of the two reverse-biased diodes is established between the circuit node N, which is the connecting point between the collector of the transistor T
1
and the source of the transistor T
2
, and ground.
These equivalent resistances may vary considerably from one example of the integrated circuit to another. This is so because of inevitable variations in manufacturing parameters and, in some cases, the potential of the node N, since a given supply voltage VDD may reach quite high values. Situations may therefore arise in which the voltage between the node N, that is, between the source terminal of the transistor T
2
and the gate terminal of the transistor, approach or reach the breakdown voltage of the gate dielectric.
A known measure for attempting to prevent the dangerous situation described above is that of connecting between the source and gate terminals of the VDMOS transistor a voltage-limiting device. This may be, for example, a diode which has a predetermined reverse-conduction voltage and which becomes conductive at a voltage between the source and gate and lower than that considered dangerous to the VDMOS transistor. Naturally, this approach applies not only to the current generator described above but, more generally, to the protection of VDMOS transistors in all applications in which the voltage between the source and gate may reach dangerous values. However, the voltage limiter and the respective connections take up additional area on the semiconductor chip containing the integrated circuit.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for making a VDMOS transistor in an integrated circuit of the type defined above in which the protection of the transistor does not require the use of additional area.
This object is achieved by a method for making VDMOS transistor structure comprising a VDMOS transistor and MOS transistor formed in the same active region to prevent over-voltages between the source and gate of the VDMOS transistor. More particularly, the VDMOS transistor is formed in a semiconductor layer of first conductivity type on a substrate of second conductivity type. The method may include forming a first region of first conductivity type extending into the semiconductor layer from a major surface thereof farther from the substrate; forming a second region of second conductivity type extending from the major surface into the semiconductor layer around the first region and laterally limiting the first region; forming a third region of second conductivity type extending from the major surface into the first region and defining a body region of a VDMOS transistor; forming a fourth region of first conductivity type extending from the major surface into the third region and defining a source region of the VDMOS transistor, the fourth region also defining a first channel with edges of the third region; and forming a fifth region of first conductivity type extending from the major surface into the first region, the first region and the fifth region together defining a drain region of the VDMOS transistor. The method may also include forming a sixth region of second conductivity type extending from the major surface into the first region, in contact with the second region, and delimiting a second channel with an edge of the third region. The third region and the sixth region may define source and drain regions of a MOS transistor, respectively. In addition, the MOS transistor may have a threshold voltage lower than a breakdown voltage between the source and gate of the VDMOS transistor so that the MOS transistor acts as a voltage limiter as defined and characterized.


REFERENCES:
patent: 4325180 (1982-04-01), Curran
patent: 4814288 (1989-03-01), Kimura et al.
patent: 5432371 (1995-07-01), Denner et al.
patent: 5525832 (1996-06-01), Consiglio et al.
patent: 5589405 (1996-12-01), Contiero et al.
patent: 3-205876 (1991-09-01), None

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