Variably controlled delay line for read data capture timing...

Details Variably controlled delay line for read data capture timing... Variably controlled delay line for read data capture timing...

2006-10-03

2006-10-03

Trujillo, James K. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S503000, C713S600000, C327S161000

Reexamination Certificate

active

07117382

ABSTRACT:
Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

REFERENCES:
patent: 4660197 (1987-04-01), Wrinn et al.
patent: 5537062 (1996-07-01), Mote, Jr.
patent: 5633608 (1997-05-01), Danger
patent: 5900762 (1999-05-01), Ramakrishnan
patent: 5955894 (1999-09-01), Vishwanthaiah et al.
patent: 5999978 (1999-12-01), Angal et al.
patent: 6043694 (2000-03-01), Dortu
patent: 6060907 (2000-05-01), Vishwanthaiah et al.
patent: 6064656 (2000-05-01), Angal et al.
patent: 6085033 (2000-07-01), Starr et al.
patent: 6212511 (2001-04-01), Fisher et al.
patent: 6253333 (2001-06-01), Bogumil et al.
patent: 6278306 (2001-08-01), Ang et al.
patent: 6281729 (2001-08-01), Ang et al.
patent: 6294924 (2001-09-01), Ang et al.
patent: 6297677 (2001-10-01), Ang et al.
patent: 6316957 (2001-11-01), Ang et al.
patent: 6339351 (2002-01-01), Ang et al.
patent: 6366139 (2002-04-01), Ang et al.
patent: 6407963 (2002-06-01), Sonoda et al.
patent: 6420913 (2002-07-01), Ang et al.
patent: 6424198 (2002-07-01), Wolford
patent: 6467043 (2002-10-01), LaBerge
patent: 6600681 (2003-07-01), Korger et al.
patent: 6622256 (2003-09-01), Dabral et al.
patent: 6695783 (2004-02-01), Henderson et al.
patent: 6738880 (2004-05-01), Lai et al.
patent: 6963989 (2005-11-01), Cullum et al.
patent: 2001/0052057 (2001-12-01), Lai et al.
patent: 2003/0001651 (2003-01-01), La Rosa
patent: 2004/0123173 (2004-06-01), Emberling et al.
patent: 2004/0225976 (2004-11-01), Cheung et al.

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