Variable width offset spacers for mixed signal and system on...

Details Variable width offset spacers for mixed signal and system on... Variable width offset spacers for mixed signal and system on...

2006-11-03

2008-11-25

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S283000, C438S595000, C257SE21051, C257SE21457, C257SE21626

Reexamination Certificate

active

07456066

ABSTRACT:
MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.

REFERENCES:
patent: 5021354 (1991-06-01), Pfiester
patent: 2007/0114605 (2007-05-01), Dyer et al.

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