Variable voltage data buffers

Details Variable voltage data buffers Variable voltage data buffers

2002-05-29

2004-02-24

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S029000, C327S170000

Reexamination Certificate

active

06696860

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-31020, filed on Jun. 2, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
FIG. 1
is a circuit diagram of a conventional data output buffer for an integrated circuit device. Referring to
FIG. 1
, the data output buffer includes a data transmission circuit
10
, a pre-driver circuit
11
, and an output driver circuit
17
. The data transmission circuit
10
includes transmission gates T
1
and T
2
, latch circuits
3
and
5
, and inverters
1
and
7
.
The transmission gate T
1
outputs data DATA to the pre-driver circuit
11
in response to assertion (for example, to a logic “high”) of a transmission control signal BUF, and the transmission gate T
2
outputs inverted data {overscore (DATA)} to the inverter
7
in response to assertion of the transmission control signal BUF.
The latch circuit
3
, which includes inverters I
1
and I
2
connected in series, and the latch circuit
5
, which includes inverters I
3
and I
4
connected in series, latch output signals of the transmission gates T
1
and T
2
.
The pre-driver circuit
11
includes inverters
13
and
15
, and the inverter
13
outputs a signal that swings between a first voltage (i.e., a first supply voltage) VDDP and a second voltage VSSP (i.e., a ground voltage) in response to the output signal of the transmission gate T
1
, and the inverter
15
outputs a signal that swings between the first voltage VDDP and the second voltage VSSP in response to an output signal of the inverter
7
. In general, the first voltage VDDP is 3.3V or 2.5V, and the second voltage VSSP is a ground voltage.
The output driver circuit
17
includes a pull-up circuit MP
1
and a pull-down circuit MN
1
. The pull-up circuit MP
1
is implemented by a PMOS transistor MP
1
and pulls up an output terminal OUT to a third voltage VDDQ (e.g., a second supply voltage) in response to an output signal UP of the inverter
13
. The pull-down circuit MN
1
is implemented by an NMOS transistor MN
1
and pulls down the output terminal OUT to a fourth voltage VSSQ (e.g., a ground voltage) in response to an output signal DOWN of the inverter
15
. Thus, the output terminal OUT swings between the third voltage VDDQ and the fourth voltage VSSQ.
In general, in order to reduce skew during transition to logic “high” or logic “low” of the signal at the output terminal OUT, “turn-on” resistance (hereinafter, referred to as “Ron_mp
1
”) of the PMOS transistor MP
1
and “turn-on” resistance (hereinafter, referred to as “Ron_mn
1
”) of the NMOS transistor MN
1
can be equalized by controlling the ratio of the channel length and the channel width of the PMOS transistor MP
1
and the NMOS transistor MN
1
.
However, in a case where the third voltage VDDQ is lower than the first voltage VDDP, for example, in a case where the first voltage VDDP is 2.5V and the third voltage VDDQ is 1.8V, the “turn-on” voltage between the gate and the source of the PMOS transistor MP
1
may be reduced, e.g., to 1.8V such that the “turn-on” resistance (Ron_mp
1
) of the PMOS transistor MP
1
is undesirably high. However, the signal DOWN input to a gate of the NMOS transistor MN
1
swings between the first voltage VDDP and the second voltage VSSP, and thus, the “turn-on” voltage between the gate and the source of the NMOS transistor MN
1
is relatively high, even though the third voltage VDDQ is lower than the first voltage VDDP. As a result, a transition slope from logic “low” to logic “high” and a transition slope from logic “high” to logic “low” of the signal of the output terminal OUT become different, and thus, skew may occur in the signal at the output terminal OUT.
FIG. 2A
illustrates output waveforms at the output terminal OUT in a case where the first voltage VDDP is the same as the third voltage VDDQ. In this case, “turn-on” resistance (Ron_mn
1
) of the NMOS transistor MN
1
and “turn-on” resistance (Ron_mp
1
) of the PMOS transistor MP
1
are the same. Thus, skew does not occur between the transition of the signal of the output terminal OUT from logic “low (0V)” to logic “high” OUT “H” and the transition from logic “high (2.5V)” to logic “low” OUT “L”.
FIG. 2B
illustrates output waveforms at the output terminal OUT in a case where the first voltage VDDP is different from the third voltage VDDQ. In this case, the “turn-on” resistance (Ron
−
mn
1
) of the NMOS transistor MN
1
and the “turn-on” resistance (Ron_mp
1
) of the PMOS transistor MP
1
are different. Thus, skew occurs between transition from logic “0V” to logic “OUT “H”” and transition from logic “1.8” to logic “OUT “L””.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention, a data buffer circuit comprises first and second driver circuits operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to the first and second data signals. The data buffer circuit also comprises an output circuit comprising first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of third and fourth voltages responsive to respective ones of the outputs of the first and second driver circuits. The data buffer circuit further comprises a transition compensation circuit operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.
In some embodiments of the present invention, the transition compensation circuit comprises a driver circuit, e.g., an inverter, coupled in series with an input of one of the first and second driver circuits, and a bias control circuit coupled to a power supply input of the driver circuit and operative to vary an impedance between the power supply input and a power supply node responsive to the transition rate control signal. In further embodiments, the transition compensation circuit comprises a selective impedance reduction circuit operative to selectively provide an impedance in parallel with at least one of the first and second transistors of the output circuit responsive to the control signal. The data buffer circuit may also include a transition rate control signal generating circuit operative to generate the transition rate control signal responsive to, for example, a state of a fuse or comparison of one of the first and second voltages to a reference voltage.


REFERENCES:
patent: 4959562 (1990-09-01), Ootani
patent: 5841305 (1998-11-01), Wilson
patent: 6157204 (2000-12-01), Sher et al.
patent: 535873 (1993-04-01), None
patent: 1999-0006314 (1999-01-01), None
patent: 2000-0003736 (2000-01-01), None
Interface Techniques—High Speed CMOS Design Styles, Chapter 6, pp. 207-246, No Date.
Notice to Submit Response, Korean Application No. 10-2001-0031020, Feb. 27, 2003.

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