Variable test voltage circuits and methods for ferroelectric mem

Static information storage and retrieval – Read/write circuit – Testing

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365145, G11C 700

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active

06055200&

ABSTRACT:
Variable test voltage circuits and methods are provided for ferroelectric memory devices. The ferroelectric memory devices include a first bit line, a word line, a nonvolatile memory cell at an intersection of the first bit line and the word line, a second bit line corresponding to the first bit line and a sense amplifier connected between the first and second bit lines to sense a voltage difference between the first and second bit lines. Test circuits and methods receive a variable test voltage and force at least one of the first and second bit lines to the variable test voltage in response to control signals during a test mode of operation. The ferroelectric memory may also include a reference cell including a ferroelectric capacitor, wherein the reference cell supplies a reference voltage to the second bit line. The test circuits and methods also may be responsive to deselection of the word line to force the first bit line to the variable test voltage. The test circuits and methods also may be responsive to deselection of the reference cell to force the second bit line to the variable test voltage. The test circuits and methods also may be responsive to control signals during a test mode of operation to receive first and second variable test voltages and force the first and second bit lines to the first and second test voltages respectively, in response to deselection of the nonvolatile memory cell and the reference cell to thereby supply the first and second bit lines with the first and second test voltages.

REFERENCES:
patent: 4800332 (1989-01-01), Hutchins
patent: 5677865 (1997-10-01), Seyyedy
patent: 5751628 (1998-05-01), Hirano et al.
patent: 5959922 (1999-09-01), Jung

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