Variable self-time scheme for write recovery by low speed...

Details Variable self-time scheme for write recovery by low speed... Variable self-time scheme for write recovery by low speed...

2005-08-23

2005-08-23

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

06934899

ABSTRACT:
In accordance with the objectives of the invention a new method is provided for testing DRAM cells using a slow-speed tester. An adjustable self-time scheme is provided that is used for write-recovery during the testing of DRAM devices using a low-speed tester. CSL and WL pulses are self-time controlled and are in this manner used to emulate DRAM operation under different operational conditions. The adjustable self-time scheme of the invention can be used to screen write recovery (twr) depending on field requirements for the DRAM cell, a low-speed tester can be used for the screening.

REFERENCES:
patent: 5896399 (1999-04-01), Lattimore et al.
patent: 6151270 (2000-11-01), Jeong
patent: 6230292 (2001-05-01), Duesman et al.
patent: 6237115 (2001-05-01), Ting et al.
patent: 6334174 (2001-12-01), Delp et al.
patent: 2001/0008488 (2001-07-01), Shinozaki

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