Variable layout design for multiple voltage applications

Details Variable layout design for multiple voltage applications Variable layout design for multiple voltage applications

2005-06-07

2005-06-07

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S203000

Reexamination Certificate

active

06903389

ABSTRACT:
An integrated circuit it comprises a logic cell. The logic cell is without nwell contacts and comprises top and bottom voltage supply wires. The integrated circuit also comprises a first filler cell comprising top and d bottom voltage supply wires and an nwell region coupled to the bottom voltage supply wire. The integrated circuit further comprises a second filler cell with an nwell region coupled to a top voltage supply wire. The integrated circuit still further comprises a third filler cell comprising top and bottom voltage supply wires. The third filler cell also comprising a pair of nwell regions. One of nwell regions is coupled to the top voltage supply wire and the other nwell region is coupled to the bottom voltage supply wire. The standard cell and the filler cells each comprise a PRboundary overlapping a top portion of the nwell region in each cell by a first distance.

REFERENCES:
patent: 2004/0251501 (2004-12-01), Catalasan et al.
Kakerow, R., “Low Power Design Methodologies for Mobile Communication,” Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI Computers and Processors (2002) 6 pages.
PURI, R., et al., “Pushing ASIC Performance in a Power Envelope,” DAC, Anaheim, CA (Jun. 2-6, 2003) pp. 788-793.
Usami, K., et al., “Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages,” Proceedings of the Design Automation Conference (Jan. 2000) pp. 123-128.

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