Variable domain redundancy replacement configuration for a memor

Details Variable domain redundancy replacement configuration for a memor Variable domain redundancy replacement configuration for a memor

1997-07-16

1999-11-02

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 5, 714 6, 714 11, G11C 700

Patent

active

059789310

ABSTRACT:
A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

REFERENCES:
patent: 5295101 (1994-03-01), Stephen et al.
patent: 5357612 (1994-10-01), Alaiwan
patent: 5430679 (1995-07-01), Hiltebeitel et al.
patent: 5459690 (1995-10-01), Rieger et al.
patent: 5461587 (1995-10-01), Oh
patent: 5475648 (1995-12-01), Fujiwara
patent: 5491664 (1996-02-01), Phelan
patent: 5691945 (1997-11-01), Liou et al.
patent: 5703817 (1997-12-01), Shiratake et al.
patent: 5724295 (1998-03-01), Beiley et al.
patent: 5831913 (1998-11-01), Kirihata
patent: 5831914 (1998-11-01), Kirihata
H. L. Kalter, et al, "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and O-Chip ECC" IEEE Journal of Solid-State Circuits, V. 25, Oct. 1990, pp. 1118-1128.
T. Kirihata, et al, "A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power" IEEE Journal of Solid-State Circuits, V. 27, Sep. 1992, pp. 1222-1228.
T. Sugibayashi, et al, "A 30ns 256Mb DTAM with Multi-Divided Array Structure" IEEE Journal of Solid-State Circuits, V. 28, Nov. 1993, pp. 1092-1098.
T. Kirihata, et al, "Fault-Tolerant Designs for 256 Mb DRAM" IEEE Journal of Solid-State Circuits, V. 31, Apr. 1996, pp. 558-566.

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