Variable-delay interconnect structure for a programmable logic d

Details Variable-delay interconnect structure for a programmable logic d Variable-delay interconnect structure for a programmable logic d

1998-04-01

1999-12-28

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 37, 326 41, 326 38, G06F 738

Patent

active

060086661

ABSTRACT:
Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal propagation delays for selected signal paths can be precisely adjusted either while the PLD is being programmed or while the PLD is operating as a logic device. The delays are adjusted by selectively connecting otherwise unused interconnect lines to the signal path to increase the capacitive load on the interconnect lines that define the signal path. The ability to control the load on selected signal paths advantageously enables a user to precisely match the signal propagation delays of two or more signal paths. In one embodiment, the loads of selected signal paths can be modified while the FPGA is operational.

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