Variable capacitances for memory cells within a cell group

Details Variable capacitances for memory cells within a cell group Variable capacitances for memory cells within a cell group

2002-06-04

2004-05-04

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S149000

Reexamination Certificate

active

06731529

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to chained architecture in memory integrated circuits (ICs). More particularly, the invention relates to ferroelectric memory ICs having a series or chained architecture.
BACKGROUND OF THE INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials including strontium bismuth tantalate (SBT) can also be used.
FIG. 1
shows a conventional ferroelectric capacitor
101
. As shown, the capacitor comprises a ferroelectric metal ceramic layer
150
sandwiched between first and second electrodes
110
and
120
. The electrodes typically are formed from a noble metal such as platinum. Other conductive materials, such as strontium ruthenium oxide (SRO), are also useful to form the electrodes. The ferroelectric capacitor uses the hysteresis polarization characteristics of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 2
shows a schematic diagram of a group of memory cells
202
which, for example, is part of an IC. The group of memory cells comprises a plurality of ferroelectric memory cells
240
1
-
240
x
, each having a transistor
242
coupled to a ferroelectric storage capacitor
244
in parallel. The group of memory cells are coupled in series to form a memory chain. Chained memory architecture is described in, for example, Takashima et al., Symposium on VLSI Circuits (1997), which is herein incorporated by reference for all purposes. The gates of the transistors, for example, are gate conductors which either serve as wordlines or are coupled to wordlines of the memory array. A bitline
250
is coupled to a first end of the chain via a selection transistor
225
and a plateline
260
is coupled to a second end of the chain.
To read data from a memory cell of a memory chain, the selection transistor of the selected memory chain is activated or rendered conductive, coupling the selected memory chain to the bitline. In addition, a pulse is provided on the plateline and all transistors except the one associated with the selected memory cell of the chain is kept active. A charge stored in the selected memory cell is transferred to the bitline. This signal is compared to a reference signal by a sense amplifier.
However, the charge in the selected capacitor is shared by the sum of the bitline capacitance
230
and total parasitic capacitances
248
of the memory cells between it and the bitline. For example, if memory cell
240
3
is selected, the charge in capacitor
244
3
is shared by the sum of the bitline capacitance and the parasitic capacitances (“load”) of memory cells
240
1
and
240
2
. The load capacitance for a memory cell varies depending on the position of the memory cell within the chain, creating a load imbalance. Cells closer to the bitline have smaller load capacitances compared to those farther away. Such imbalance causes a variation in the bitline signal depending on the memory cell selected, which is undesirable as this reduces the sensing window of the sense amplifier.
From the foregoing discussion, it is desirable to provide a chained architecture which avoids the adverse effects of the intrinsic load imbalance.
SUMMARY OF THE INVENTION
The invention relates to integrated circuits with chained memory architectures having, for example, ferroelectric memory cells. In accordance with the invention, the capacitors of the memory cells within a chain have different capacitances to compensate for the intrinsic load differences experienced by the different memory cells. This enables all the memory cells of the chain to have an effective capacitance which is about the same, thereby increasing sensing window which results in increased yield and performance.


REFERENCES:
patent: 6366490 (2002-04-01), Takeuchi et al.
patent: 6473330 (2002-10-01), Ogiwara et al.
patent: 6483737 (2002-11-01), Takeuchi et al.
patent: 6552922 (2003-04-01), Ogiwara et al.

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