Valuation of tester accuracy

Details Valuation of tester accuracy Valuation of tester accuracy

2000-02-22

2003-04-22

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S073100

Reexamination Certificate

active

06553522

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to valuation of tester accuracy, in particular to quantitative measure of the effect of tester accuracy on yield and escapes for semiconductor components.
2. The Prior Art
Semiconductor component testers are used to test the performance of a device under test (DUT) under specified operating conditions, such as at a particular clock speed. The less accurate a tester is, the harder it is to tell whether a device under test (DUT) is capable of running at speed or not. This uncertainty increases when the DUT speed increases. The uncertainty has a probability of its own that is comprised of multiple parameters involving the DUT design, the DUT manufacturing process and the tester. For most applications, testers have been accurate enough to achieve credible judgements about the DUT speed. The price for misjudgment hasn't been very critical either. In the microprocessor world however, manufacturers could charge price premiums for their faster parts, which drives the needs for better tester accuracy in those markets. As memory interface standards evolve, the requirements for tester data rates and accuracy are increasing. Rambus Inc. of Mountain View, Calif. USA (Rambus) in particular is requiring speed three or more times the current testers' basic rates. Maintaining accuracy on a set of pins within tight accuracy limits becomes very challenging. Methods for valuation of the accuracy of a tester are desirable.
SUMMARY OF THE INVENTION
The description below shows that these challenges are worth every dollar spent on the tester technology. The description starts with assumptions and the theoretical model, then details the results for exemplary Rambus timing parameters and ends with an economic model. The description demonstrates that the impact on the end memory manufacturers' bottom line is too great to be tolerated.
In one form of the invention, methods are provided for comparing a first semiconductor component tester having a first overall tester accuracy with a second semiconductor component tester having a second overall tester accuracy, comprising: calculating actual yield of the first semiconductor component tester for a given set of input parameters; calculating actual yield of the second semiconductor component tester for the given set of input parameters; comparing the actual yield of the first semiconductor component tester with the actual yield of the second semiconductor component tester. The actual yields may be displayed versus tester accuracy. The input parameters may be selected from a group comprising: Ideal Yield, Absolute Limit, Acceptable Defects Per Million, and Tester Edge Placement Accuracy. Economic value of the difference between the calculated actual yield of the first semiconductor component tester and the calculated actual yield of the second semiconductor component tester can be determined.
Also provided in accordance with embodiments of the invention are methods of estimating actual yield of a semiconductor device tester, comprising: setting input parameters, including an acceptable defect rate; assuming a normal distribution of signal edge placement versus time, calculate standard deviation of signal edge placement (&sgr;_dut) about the mean signal edge placement (&mgr;_dut); initializing a test limit; calculating an expected defect rate; and calculating actual yield. The input parameters may further include: Ideal Yield, Absolute Limit, and Tester Edge Placement Accuracy. The methods may also comprise: comparing the expected defect rate with the acceptable defect rate and, if the provisional defect rate differs from the acceptable defect rate, changing the test limit and recalculating the expected defect rate. The input parameters may include an Absolute Limit and initializing the test limit may comprise setting the test limit equal to the Absolute Limit. Calculating actual yield may comprise calculating the probability that a signal edge transition of a semiconductor device will occur within a tester edge uncertainty limit.
Also provided in accordance with embodiments of the invention are computer program products and computer systems with program code for performing such methods.


REFERENCES:
patent: 6192496 (2000-02-01), Lwarenence et al.
Charoen et al., Adaptive Enhancement of Timing Accuracy and Waveform Quality in High-Performance IC Testers, 1992, IEEE vol. 39, No. 2, p. 139-151.*
Dahlberg, B., Increasing Test Accuracy by Varying Driver Slew Rate, 1991, IEEE, p. 44-48.*
Alcorn, B., Writing Correct and Usable Specifications for Board Test: A Case study, 1989, IEEE, p. 773-786.*
SEMI draft document #2928, Specification for overall digital timing accuracy, section 7.1 (SEMI G79-0200 Specification for Overall Digital Timing Accuracy, Semiconductor Equipment & Materials International, Mountain View, California, §7.1 (5 pages).

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