Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-09-13
2005-09-13
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S780000, C438S782000, C438S795000, C977S726000
Reexamination Certificate
active
06943117
ABSTRACT:
A UV nanoimprint lithography process for forming nanostructures on a substrate. The process includes depositing a resist on a substrate; contacting a stamp having formed thereon nanostructures at areas corresponding to where nanostructures on the substrate are to be formed to an upper surface of the resist, and applying a predetermined pressure to the stamp in a direction toward the substrate, the contacting and applying being performed at room temperature and at low pressure; irradiating ultraviolet rays onto the resist; separating the stamp from the resist; and etching an upper surface of the substrate on which the resist is deposited. The stamp is an elementwise embossed stamp that comprises at least two element stamps, and grooves formed between adjacent element stamps and having a depth that is greater than a depth of the nanostructures formed on the element stamps.
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Jeong Jun-Ho
Lee Eung-Sug
Shin Young-Jae
Sim Young-Suk
Sohn HyonKee
Harness & Dickey & Pierce P.L.C.
Korea Institute of Machinery & Materials
Smoot Stephen W.
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