Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-02-26
2010-06-15
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07739567
ABSTRACT:
A Serializer/De-serializer (SerDes) of an integrated circuit (IC) includes selectable inputs and outputs not only for functional data and boundary scan (e.g., JTAG) test data, but also for parallel-scan test data. The serializing portion of the SerDes includes multiplexing logic responsive to control signals to select or identify one of the multiplexing logic inputs for functional data, boundary scan data and parallel-scan data. The de-serializing portion similarly includes selection logic responsive to such control signals to select or identify one of the selection logic outputs for functional data, boundary scan data and parallel-scan data. The multiplexing logic and selection logic couple the selected input or output, respectively, to the SerDes input/output pads.
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Vandivier Suzette D.
Volz Aaron M.
Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
Kerveros James C
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