Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-01-23
2002-09-24
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S578000, C438S440000, C438S587000, C438S966000, C438S981000
Reexamination Certificate
active
06455405
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to methods of forming dual thickness gate oxide layers.
BACKGROUND OF THE INVENTION
The current process to grow dual thickness gate oxide layers is: forming a first gate oxide on a silicon substrate; masking a portion of the first gate oxide with a photoresist layer; wet etching to remove the exposed portion of the first gate oxide; stripping the photoresist masking layer; then growing gate oxide at the wet etched silicon substrate portion and additional gate oxide at the first gate oxide portion to form dual thickness gate oxide portions of about 70 Å and about 140 Å.
U.S. Pat. No. 5,918,116 to Chittipeddi describes a dual gate oxide process that forms a thicker oxide using an amorphizing ion implantation using, for example, silicon, fluorine, arsenic and mixtures thereof.
U.S. Pat. No. 6,133,164 to Kim describes a dual oxide process using an oxygen implant.
U.S. Pat. Nos. 5,920,779 to Sun et al., U.S. Pat. No. 6,093,659 to Grider et al., U.S. Pat. No. 6,030,862 to Kepler and U.S. Pat. No. 6,165,849 to An et al. are related dual oxide and ion implantation patents.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming dual thickness gate oxide layers.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least a first area and a second area is provided. The second area of the structure is masked. Ion implanting Si
4+
or Ge
4+
ions into the unmasked first area of the structure to form an amorphous layer within the first area of the structure. The second area of the structure is unmasked. The first and second areas of the structure are oxidized to form: a first gate oxide layer upon the structure within the first area; and a second gate oxide layer upon the structure within the second area. The first gate oxide layer having a greater thickness than the second gate oxide layer, completing formation of the dual thickness gate oxide layers.
REFERENCES:
patent: 6169018 (2001-01-01), Lee
patent: 6399448 (2002-06-01), Mukhopadhyay et al.
patent: 6410991 (2002-06-01), Kawai et al.
Ackerman Stephen B.
Dang Trung
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Using implantation method to control gate oxide thickness on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Using implantation method to control gate oxide thickness on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using implantation method to control gate oxide thickness on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2820983