Using a submicron level dimension reference

Details Using a submicron level dimension reference Using a submicron level dimension reference

1997-08-06

2000-04-11

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

With measuring or testing

438 18, 257 48, 702 97, 2502521, H03L 2358

Patent

active

060487437

ABSTRACT:
A submicron level dimension reference for use with a scanning electron microscope in a semiconductor device fabrication apparatus. The reference has a first insulating layer with a first pattern formed on a semiconductor wafer substrate. A plurality of contacts are formed between the first pattern of the first insulating layer such that the contacts directly communicate the wafer substrate. The contacts are capable of carrying an electrical charge. An electrically conductive layer is formed over the contacts and the first insulating layer. A second insulating layer with a second pattern is formed over the conductive layer. Electrical charges generated by radiating the scanning electron microscope on the submicron level dimension reference are transferred from the first and second insulating layers to the wafer substrate via the conductive layer and the plurality of contacts.

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