User-configurable on-chip program memory system

Details User-configurable on-chip program memory system User-configurable on-chip program memory system

1998-12-15

2001-11-20

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S154000

Reexamination Certificate

active

06321318

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains generally to microprocessor architectures, and pertains more particularly to microprocessors having on-chip program memory capability.
BACKGROUND OF THE INVENTION
A microprocessor is a circuit that combines the instruction-handling, arithmetic, and logical operations of a computer on a single chip. A digital signal processor (DSP) is a microprocessor optimized to handle large volumes of data efficiently. Such processors are central to the operation of many of today's electronic products, such as high-speed modems, high-density disk drives, digital cellular phones, and complex automotive systems, and will enable a wide variety of other digital systems in the future. The demands placed upon DSPs in these environments continue to grow as consumers seek increased performance from their digital products.
Designers have succeeded in increasing the performance of DSPs and microprocessors in general by increasing clock speeds, by removing architectural bottlenecks in circuit designs, by incorporating multiple execution units on a single processor circuit, and by developing optimizing compilers that schedule operations to be executed by the processor in an efficient manner. As further increases in clock frequency become more difficult to achieve, designers have embraced the multiple execution unit processor as a means of achieving enhanced DSP performance. For example,
FIG. 2
shows a block diagram of the CPU data paths of a DSP having eight execution units, L
1
, S
1
, M
1
, D
1
, L
2
, S
2
, M
2
, and D
2
. These execution units operate in parallel to perform multiple operations, such as addition, multiplication, addressing, logic functions, and data storage and retrieval, simultaneously.
Theoretically, the performance of a multiple execution unit processor is proportional to the number of execution units available. However, utilization of this performance advantage depends on the efficient scheduling of operations so that most of the execution units have a task to perform each clock cycle. Efficient scheduling is particularly important for looped instructions, since in a typical runtime application the processor will spend the majority of its time in loop execution.
Unfortunately, the inclusion of multiple execution units also creates new architectural bottlenecks. Increased functionality translates into longer instructions, such as may be found in very long instruction word (VLIW) architectures. For example, the eight-execution unit VLIW processor described above may require a 256-bit instruction every clock cycle in order to perform tasks on all execution units. As it is generally neither practical nor desirable to provide, e.g., a 256-bit-wide parallel data path external to the processor merely for instruction retrieval, the data rate available for loading instructions may become the overall limiting factor in many applications. An object of the present invention is to resolve this bottleneck.
SUMMARY OF THE INVENTION
Many high performance signal processors provide at least some program memory on-chip because of the delays associated in loading instructions from external memory. However, the area on a microprocessor allotted for on-chip memory is by necessity limited, and prior art on-chip memories provide no ability to reconfigure this limited and precious resource. The present invention seeks to solve a heretofore unrecognized problem—given that the core functionality of some applications can be loaded on-chip to a sufficiently-sized memory, while the core functionality of others cannot, can an on-chip memory be designed to meet the needs of either type of application, without duplicating and possibly wasting resources? It has now been recognized that an on-chip memory that is configurable by the user, preferably in software, will provide the maximum flexibility for all applications. The present invention provides a microprocessor with an on-chip memory that may be configured at runtime to one of several memory modes as requested by an application.
In one aspect of the present invention, a microprocessor is disclosed that comprises a configurable on-chip memory. Preferably, the microprocessor further comprises a program memory controller that allows the current on-chip memory configuration to remain transparent to the microprocessor central processing unit (CPU) core during program memory operations. Preferably, the configurable on-chip memory may be configured as either memory-mapped or cache memory. The cache memory may preferably be further configured to operate in multiple modes, e.g., fully enabled, bypassed, or read-only.
In a second aspect of the invention, the configurable on-chip memory may be reconfigured during microprocessor operation under software control. For instance, a configurable memory may be booted in one mode, and subsequently switched, once or multiple times, to other modes, by software commands executed by the CPU of the microprocessor. Such software commands preferably alter the operation of the program memory controller and on-chip memory by changing a control signal on the microprocessor.
In yet another aspect of the invention, the program memory controller (PMC) operates in either a memory-mapped mode or a cache mode to determine if requested addresses are on-chip memory addresses. The program memory controller preferably supplies requested fetch packets if on-chip, or halts the processor and loads requested fetch packets from off-chip. The PMC checks for requests for memory mode transitions and initiates transitions when the CPU requests such.
In a further aspect of the present invention, a tag RAM is associated with cache memory operation. This tag RAM preferably operates in conjunction with the program memory controller, which determines if the fetch packet at the requested address is currently loaded into the cache. The program memory controller preferably has the capability to update the tag RAM when a fetch packet is loaded from off-chip. The program memory controller preferably also has the capability to re-initialize the tag RAM during microprocessor operation, e.g., due to a switch in memory configuration.


REFERENCES:
patent: 5586293 (1996-12-01), Baron et al.
patent: 5721862 (1998-02-01), Sartore et al.
patent: 5819305 (1998-10-01), Nixon

Affiliated with

Also associated with

Rating

User-configurable on-chip program memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with User-configurable on-chip program memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and User-configurable on-chip program memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2573921