Useable drop-in strategy for correct electrical analysis of semi

Details Useable drop-in strategy for correct electrical analysis of semi Useable drop-in strategy for correct electrical analysis of semi

1999-01-04

1999-11-23

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257786, 257206, H01L 2358

Patent

active

059904887

ABSTRACT:
A semiconductor wafer incorporating process control monitors and a method of incorporating the same are provided. In one aspect, the semiconductor wafer has a plurality of fields formed in a pattern thereon that is subdivided into n zones and has a center point. The semiconductor wafer is provided with a plurality of integrated circuits each of which is positioned in one of the plurality of fields. The semiconductor wafer also includes a plurality of diagnostic integrated circuits dispersed in a pattern. The pattern is such that each of the plurality of diagnostic integrated circuits is positioned in one of the plurality fields, one of the plurality of diagnostic integrated circuits is positioned in each of the n zones, and a circle of radius R from the center point will intersect at least one of the plurality of diagnostic integrated circuits where R is greater than or equal to the distance between the center point and the innermost of the plurality of diagnostic integrated circuits and less than or equal to the distance between the center point and the outermost of the plurality of diagnostic integrated circuits.

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