Use of sacrificial dielectric structure to form...

Details Use of sacrificial dielectric structure to form... Use of sacrificial dielectric structure to form...

1998-12-04

2001-03-13

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S692000, C438S585000, C438S595000, C438S719000, C438S735000

Reexamination Certificate

active

06200865

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly, to a semiconductor device having a self-aligned low-resistance gate stricture and to a method for producing this device.
2. Description of the Relevant Art
The formation of self-aligned source and drain regions is a well-established technique in MOSFET fabrication. These source and drain regions exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that limit high-frequency transistor performance. In general, the self-alignment is achieved by fabricating a gate conductor, and subsequently using the gate conductor as a mask for implantation of dopant impurities to form the source and drain. Because it is formed before the implantation and subsequent annealing of the source and drain impurities, the gate conductor must be made from a material which can withstand high-temperature processing.
The current material of choice for gate conductors in MOSFET fabrication is polycrystalline silicon, or polysilicon. Although polysilicon has good high-temperature properties, it has high resistivity compared to that of a metal. The resistance R of a material region can be defined in terms of the matcrial's resistivity, &rgr;, the region's cross-sectional area, A, and the region's length, l, using the equation R=&rgr;l/A. As features on integrated circuits become smaller, area A decreases, and it becomes more and more important for resistivity to be low in order to achieve low resistances. The resistivity of a polysilicon gate conductor is typically lowered by doping. The doping is often performed by ion implantation, using the same implants which dope the self-aligned source and drain.
Problems arise with this process, however, in part because of the different rates of dopant diffusion in polysilicon as opposed to single-crystal silicon. Although typical gate conductor thicknesses arc greater than the depths of the shallow junctions required for source and drain regions in high-performance devices, diffusion rates along the grain boundaries of polycrystalline films can be on the order of one hundred times as fast as in single-crystal silicon. This can allow dopants in a polysilicon gate conductor to diffuse across the thin gate oxide and into the underlying channel region during high-temperture processes such as implant anneals. Such diffusion can leave a region of low carrier concentration in the polysilicon directly above the gate oxide, an occurrence often called the “polysilicon depletion effect”. This region of the gate conductor adjacent to the gate dielectric therefore has a higher resistivity, and the resulting device performs as if it had an increased gate dielectric thickness. Effective doping of polysilicon gate regions is further complicated in CMOS devices because of differences in diffusion behavior of boron, the typical p-channel transistor dopant, and arsenic, the typical n-channel transistor dopant. Boron diffuses more rapidly in polysilicon than arsenic, which tends to segregate at grain boundaries. Adequate activation of arsenic impurities throughout the gate conductor of an n-channel device without causing excessive boron diffusion and polysilicon depletion effects in a p-channel device presents significant challenges.
Another problem with self-aligned process in which gate conductors are formed prior to source/drain formation is that any impurity introduction into the channel region which may be needed, such as impurities for adjusting threshold voltage, must generally be introduced early in the fabrication process, and across the entire active area of the substrate. In order to be placed in the channel region, such impurities must be introduced before formation of the gate conductor, and restricting them to a particular region of the substrate would require an additional masking step, and the expense and chance for yield reduction associated with masking steps. Problems which may result from introducing channel-region impurities across the entire active area before gate conductor formation include electrical compensation of subsequently-formed source and drain regions, and unwanted migration of the channel-region impurities during subsequent high-temperature anneals, such as those typically used to activate source/drain impurity distributions.
A gate conductor made from a low-resistance metal would alleviate many of the problems with polysilicon gate conductors discussed above. Unfortunately, low-resistance metals such as aluminum are not able to withstand the high-temperature processing needed, for example, to anneal the as-implanted source and drain regions employed within a standard self-aligned process. It would therefore be desirable to develop a method of forming self-aligned gates using low-resistance metals or metal alloys. The desired method should further allow impurities to be introduced exclusively into the channel region of a transistor.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by a process in which a metal-containing self-aligned gate structure is formed after high-temperature processes such as the source and drain anneal cycles. One or more sacrificial dielectric gate structures are formed on a semiconductor substrate. Because the sacrificial gate structure will be removed during subsequent processing, etch selectivity to the gate structure over the underlying semiconductor is important. Use of a dielectric rather than other material such as polysilicon for the sacrificial gate structure may be advantageous by allowing improved selectivity over the underlying, silicon-based semiconductor substrate. A fabrication process similar to that typically used to form polysilicon-gate transistors is subsequently carried out using the sacrificial gate structure in place of a polysilicon gate. Self-aligned source and drain impurity introduction may be included in this fabrication, for example, and a salicide process may be performed on the transistors.
The sacrificial gate structure must be formed from a dielectric which can withstand the temperatures used in this fabrication process, such as the temperatures needed to anneal source and drain impurity implants, for example. Suitable dielectrics include silicon dioxide (“oxide”), silicon nitride (“nitride”), and silicon oxynitride (“oxynitride”). Dielectric spacers may be formed on sidewalls of the sacrificial gate structure as a part of the transistor fabrication process discussed above. If such spacers are formed, they must be formed from a different dielectric than that used to form the sacrificial gate structure, so that the gate structure may subsequently be removed without removing the spacers. For example, if oxide is used to form the sacrificial gate structure, nitride or oxynitride may be used to form the spacers. Alternatively, the gate structure may be formed from nitride or oxynitride, and the spacers from oxide.
Protective dielectrics are subsequently formed over the substrate and surrounding the sacrificial gate structures such that upper surfaces of the protective dielectrics are even with upper surfaces of the gate structures. In this way, all upper surfaces of the semiconductor topography except the upper surfaces of the gate structures are protected by dielectric. As in the case of the spacers described above, the protective dielectrics are formed from a different dielectric than that used to form the sacrificial gate structures. Each uncovered sacrificial gate structure is Subsequently removed by a self-aligned, selective etch process to produce a trench in place of the previously for med sacrificial date structure. A base of the trench comprises an upper surface of the underlying semiconductor substrate. Depending on the desired operating characteristics of the finalized device, this trench may subsequently be refilled with mate rial s including low-resistivity metals, dielectric layers, and/or polysilicon layers. Any material deposited external to the trench is subseque

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