Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-28
2002-10-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S636000
Reexamination Certificate
active
06458689
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of contact or via holes using an Anti-Reflection Coating and chemical-mechanical polishing processes in semiconductor devices and more particularly to the fabrication of an Anti-Reflection Coating composed of Silicon oxynitride (SiON) and chemical-mechanical polish processes used in making contact holes or via holes in ILD or IMD dielectric layers.
2) Description of the Prior Art
Chemical-mechanical polish (CMP) planarization processes are used to level dielectric layers and to polish down metal layer in semiconductor devices. However, these CMP process can create microscratches in dielectric layers that degrade photolithographic performance and create defects. The inventor(s) have found the following problems as described below and in
FIGS. 8A
to
8
D. This is not prior art for the patentability of the invention.
FIG. 8A
shows the chemical-mechanical polishing
209
of a dielectric layer
214
overlying a metal line
211
on a substrate
10
.
FIG. 8B
shows the microscratches
216
the inventor has noticed after the chemical-mechanical polish.
Next, an organic bottom anti-reflective coating (BARC) layer
218
and a photoresist layer
224
are formed over the dielectric layer
214
and the microscratches
216
. The organic BARC layer
218
and a photoresist layer
224
are exposed to create a photoresist opening
225
(shown as dashed lines).
A problem the inventor has noticed is that the microscratches create reflections that degrade the photoresist pattern.
Next, a via hole is etched in the dielectric layer
214
as shown in FIG.
8
C. The photoresist layer is removed.
As shown in
FIG. 8C
, a barrier layer
228
and metal layer
230
are formed over the dielectric layer and fill the via hole. The barrier layer and metal layer fill in some of the microscratches.
FIG. 8D
shows the CMP of the metal layer and barrier layer to form the metal plug
323
. However, the microscratches
216
are filled with metal and barrier layer
228
. These filled microscratches create defects, short with overlying conductive lines and create photo defects.
Moreover, new microscratches
245
are formed in the dielectric layer by the metal CMP. These new metal chemical-mechanical polish created microscratches
245
cause similar problems.
Therefore, there is a need for a method to prevent microscratches in dielectric layers formed during contact/via hole formation and contact plug/via plug CMP processes.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,766,974 (Sardella)—Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric—that shows an integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer. U.S. Pat. No. 5,767,018 (Bell) shows polysilicon etch process using an ARC layer. U.S. Pat. No. 5,354,712 (Ho)Method for forming interconnect structures for integrated circuits—teaches dielectric layer that is chemical-mechanical polished. U.S. Pat. No. 5,674,784 (Jang et al.) shows a method of forming a polish stop for a CMP process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of covering microscratches created by a chemical-mechanical polishing of a dielectric layer using a SiON layer.
It is an object of the present invention to provide a method provides a method of preventing/filling microscratches in a dielectric layer created by a chemical-mechanical polishing of a conductive layer in a contact or via plug formation process using a dielectric Anti-Reflection Coating (DARC) SiON layer.
To accomplish the above objectives, the present invention provides a method forming a protective dielectric anti-reflective coating (DARC) layer composed of Silicon oxynitride (SiON) or a Plasma enhanced oxide (PE-oxide) layer
20
over a dielectric layer after a chemical-mechanical polish planarization and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. The invention has two embodiments for the composition of the protective DARC layer (1) SiON and (2) PE-Oxide. A invention's method of forming a protective Silicon oxynitride (SiON) dielectric anti-reflective coating (DARC) or PE-oxide DARC for a contact or via opening includes the following.
A dielectric layer is formed over a semiconductor structure. The dielectric layer is chemical-mechanical polished whereby the chemical-mechanical polish creates microscratches in the dielectric layer. The invention's key protective dielectric anti-reflective coating (DARC) layer (SiON or PE-Ox) is formed over the dielectric layer whereby the protective dielectric layer fills in the microscratches in the dielectric layer. The SiON DARC layer is formed using a plasma enhanced chemical vapor deposition process. A photoresist layer is formed over the dielectric anti-reflective coating (DARC) layer. The photoresist layer is exposed and developed to create a first resist opening. The SiON DARC layer and the dielectric layer are etched through the first resist opening to form a first opening. The first opening can expose a contact area on the substrate or a conductive line over the substrate. The photoresist layer is then removed. A conductive (e.g., metal) layer is formed over the SiON DARC layer and fill the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the SiON DARC layer and to form an interconnect filling the first opening. The SiON DARC layer is used as a CMP stop whereby the SiON DARC layer prevents microscratches in the dielectric layer. The element numbers in the summary of the invention do not limit the scope of the claimed invention but only allow a better understanding of the general invention. In the description above, the Invention's protective layer can alternatively be composed of PE-oxide.
The Invention Provides the Following Benefits
The invention's protective SiON or PE-oxide DARC layer provides superior anti-reflective characteristics especially when applied to deep ultra violet (DUV) photo processes. The invention's DARC layer eliminates the need to use an organic BARC. The inventor has found that compared to a Organic BARC, SiN ARC layer or oxide layer not formed using a plasma enhanced process, the invention SiON and PE-Ox layer has unexpected superior anti-reflective characteristics and scratch filling properties.
Moreover, the invention's DARC layer fills in microscratches in dielectric layer from previous chemical-mechanical polishing planarization processes.
The invention's SiON DARC layer also is a superior CMP stop layer for the metal fill CMP. The protective DARC layer prevents microscratches form chemical-mechanical polish processes.
In all these aspects, the invention's SiON layer is superior to a Silicon nitride layer or a SiN/SiON Stack or a oxide not formed using a PE process.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5674784 (1997-10-01), Jang et al.
patent: 5766974 (1998-06-01), Sardella et al.
patent: 5767018 (1998-06-01), Bell
patent: 5886410 (1999-03-01), Chiang et al.
patent: 6077784 (2000-06-01), Wu et al.
patent: 6114325 (2000-09-01), Foote et al.
Jang Syun-Ming
Shih Tsu
Twu Jih-Chuyng
Yen Anthony
Yu Chen-Hua
Ackerman Stephen B.
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
LandOfFree
Use of PE-SiON or PE-Oxide for contact or via photo and for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of PE-SiON or PE-Oxide for contact or via photo and for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of PE-SiON or PE-Oxide for contact or via photo and for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2926233