Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-18
1999-01-12
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438370, 438526, 438509, 438950, 257565, H01L 2174, H01L 2122, H01L 218222, H01L 21265
Patent
active
058588280
ABSTRACT:
High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.
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patent: 4732869 (1988-03-01), Van Attekum et al.
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patent: 5160996 (1992-11-01), Odanaka
patent: 5436176 (1995-07-01), Shimizu et al.
patent: 5501993 (1996-03-01), Borland
Characteristics of Bipolar Transistors with Various Depths of n+ Buried Layers Formed by High-Energy Ion Implantation, Akihiro Tamba, Yutaka Kobayashi, Tadeshi Suzuki and Nobuyoshi Natsuaki, Japanese Journal of Applied Physics pp. 156-160, Dec. 1991.
Tamba A et al: Characteristics of Bipolar Transistors with Various Depth N+ Buried Layers Formed by High Energy Ion Implantation; Extended Abstracts of the International Conference on Solid State Devices and Materials; Tokyo, Aug. 24-26, 1988; No. Conf. 20, 24 Aug. 1988, Japan Society of Applied Physics; pp. 141-144; XP000042517.
Daniel David W.
Randazzo Todd A.
Seliskar John J.
Bailey Wayne P.
Chaudhuri Olik
Coleman William David
Symbios, Inc.
Yee Duke W.
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