Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-31
2003-05-20
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S217000, C438S275000, C438S279000, C438S289000, C438S525000
Reexamination Certificate
active
06566204
ABSTRACT:
FIELD OF USE
This invention relates to the fabrication and structure of field-effect transistors (“FETs”) of the insulated-gate type. All of the insulated-gate FETs (“IGFETs”) described below are enhancement-mode devices except as otherwise indicated.
BACKGROUND
An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone that extends between a source and a drain. The channel zone in an enhancement-mode IGFET is part of a body region that forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all semiconductor body material between the source and drain.
FIG. 1
illustrates a conventional symmetrical n-channel enhancement-mode IGFET
10
provided with a two-part drain for reducing undesired hot-carrier injection. IGFET
10
is created from a monocrystalline silicon semiconductor body having region
12
of lightly doped p-type body material. IGFET
10
has n-type source
14
, n-type drain
16
, intervening p-type channel zone
18
, gate electrode
20
, gate dielectric layer
22
, and gate sidewall spacers
24
and
26
. Drain
16
consists of heavily doped main portion
16
M and more lightly doped extension
16
E. Source
14
similarly consists of heavily doped main portion
14
M and more lightly doped extension
14
E. When IGFET
10
is turned on, electrons travel from source
14
to drain
16
by way of a thin channel induced in channel zone
18
along the upper semiconductor surface.
A pair of depletion regions extend respectively along the drain/body and source/body junctions. Under certain conditions, especially when the channel length is small, the drain depletion region can extend laterally to, and merge with, the source depletion region. This phenomenon is termed punchthrough. If the drain depletion region punches through to the source depletion region, the operation of IGFET
10
cannot be controlled with gate electrode
20
. Accordingly, punchthrough normally needs to be avoided.
One conventional technique for inhibiting punchthrough in an IGFET as channel length is reduced, and also for alleviating roll-off of the threshold voltage at short channel length, is to increase the net dopant concentration of the channel zone in a pocket along the source. See Ogura et al, “A Half Micron MOSFET Using Double Implanted LDD,”
IEDM Tech. Dig
., Int'l Elec. Devs. Meeting, Dec. 11-15, 1982, pages 718-721. As an artifact of creating the increased-concentration pocket along the source, the dopant concentration in the channel zone is commonly increased in a corresponding pocket along the drain. Per Codella et al, “Halo Doping Effects in Submicron DI-LDD Device Design,”
IEDM Tech. Dig
., Int'l Elec. Devs. Meeting, Dec. 1-4, 1985, pages 230-233, the pockets are commonly referred to as “halo”.
FIG. 2
depicts a conventional symmetrical n-channel enhancement-mode halo IGFET
30
as configured in Ogura et al or Codella et al. Except as described below, IGFET
30
contains the same regions as IGFET
10
in FIG.
1
. As shown in
FIG. 2
, channel zone
18
in n-channel IGFET
30
includes a pair of p-type halo pockets
31
and
32
doped more heavily than the remainder of channel zone
18
. Halo pockets
31
and
32
are situated along the inner boundaries of source
14
and drain
16
so as to inhibit punchthrough. Metal silicide layers
33
,
34
, and
35
respectively contact components
14
M,
16
M, and
20
. Portion
36
of channel zone
18
contains ion-implanted p-type threshold-adjust dopant.
Halo pockets
31
and
32
can be created in various ways. For example, p-type halo dopant is typically ion implanted through the upper semiconductor surface into the semiconductor body using gate electrode
20
as an implantation shield. The halo implant can be performed roughly perpendicular to the upper semiconductor surface as indicated in Ogura et al.
The halo implant can also be performed at a substantial angle to a perpendicular to the upper semiconductor surface. In this regard, see (a) Su, “Tilt Angle Effect on Optimizing HALO PMOS Performance,” 1997 Int'l Conf. Simulation Semicon. Procs. and Devs., Sep. 8-10, 1997, pages 33-36, (b) Rodder et al, “A Sub-0.18 &mgr;m Gate Length CMOS Technology for High Performance (1.5 V) and Low Power (1.0 V),”
IEDM Tech. Dig
., Int'l Elec. Devs. Meeting, Dec. 8-11, 1996, pages 563-566, and (c) Hori, “A 0.1-&mgr;m CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS),”
IEDM Tech. Dig
., Int'l Elec. Devs. Meeting, Dec. 11-14, 1994, pages 75-78.
As indicated above, a halo pocket is needed only at the source to alleviate the short-channel effects of punchthrough and threshold voltage roll-off. In fact, having a halo pocket at the drain can increase the threshold voltage and lower the drive current. Consequently, the performance of symmetrical IGFET
30
can be less than what would occur if halo pocket
32
were not present along drain
16
.
FIG. 3
depicts a conventional asymmetrical n-channel enhancement-mode halo IGFET
38
configured as described in Hwang, U.S. Pat. No. 5,364,807, so as to have a halo pocket only along the source. Except as described below, IGFET
38
contains the same regions as IGFET
10
in FIG.
1
. As illustrated in
FIG. 3
, halo pocket
31
is situated along source
14
in IGFET
38
. IGFET
38
does not have a halo pocket along drain
16
. With gate dielectric layer
22
extending laterally beyond gate electrode
20
, IGFET
38
has gate sidewall spacer
26
along the drain side of electrode
20
but lacks a sidewall spacer along the source side of electrode
20
.
FIG. 4
illustrates how halo pocket
31
is formed along source
14
without forming a corresponding halo pocket along drain
16
. A source-side gate sidewall spacer is utilized in creating source
14
. After source
14
and drain
16
are formed, a photoresist mask
39
having a opening above the source-side spacer is provided along the upper surface of the structure. The source-side spacer is removed. P-type dopant is ion implanted vertically through the mask opening to define source-adjoining halo pocket
31
. Mask
39
and drain-side spacer
26
prevent a corresponding halo pocket from being formed along drain
16
.
While the asymmetrical structure of IGFET
38
can enhance device performance, the technique utilized to create source-adjoining halo pocket
31
without creating a drain-adjoining halo pocket requires an extra masking step. This is disadvantageous since masking operations tend to be relatively costly. The photolithographic layout of mask
39
has to be very accurate because the opening in mask
39
needs to overlie the source-side spacer. Also, it is typically desirable to provide metal silicide regions along components
14
,
16
, and
20
at a point near the end of the IGFET fabrication process. Since a source-side gate sidewall spacer is not present in the final structure of IGFET
38
, attempting to provide such metal silicide regions can result in the metal silicide along gate electrode
20
bridging to the metal silicide along source
14
. Consequently, electrode
20
can be electrically shorted to source
14
, thereby making IGFET
38
useless as a switching device.
Other techniques have been investigated for creating asymmetrical IGFETs in which a halo pocket is present along the source but not along the drain. For example, see Buti et al, “Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half Micron n-MOSFET Design for Reliability and Performance,”
IEDM Tech. Dig
., Int'l Elec. Devs. Meeting, Dec. 3-6, 1989, pages 617-620. In general, each of these other techniques requires an additional masking operation or/and incurs other disadvantages. It is desirable to create an asymmetrical IGFET so that its channel zone is doped more heavily along the source than along the drain without necessitating any additional masking operation and without causing performance degradation.
GENERAL DISCLOSURE OF THE INVENTION
The present invention utilizes a combination of mask shadowing a
Bulucea Constantin
Wang Fu-Cheng
Meetin Ronald J.
National Semiconductor Corporation
Pham Long
Skjerven Morrill LLP
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