Use of functional memory cells as guard cells in a...

Details Use of functional memory cells as guard cells in a... Use of functional memory cells as guard cells in a...

1999-05-20

2001-07-10

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S256000, C438S261000, C438S655000, C365S051000, C365S189050, C365S189050, C365S230010

Reexamination Certificate

active

06258642

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and in particular, to organization and layout thereof.
2. Description of the Related Art
In the sub-micron regime of semiconductor lithographic processes, the proximity of adjacent features can have a profound effect on the size and shape of a given feature. A very noticeable effect occurs, for example, in the channel length of a metal-oxide-silicon transistor (i.e., MOS transistor), depending on the spacing to the neighboring polysilicon (i.e. “poly”) feature.
In the design of SRAM circuits, it is desirable to have the smallest physical cell possible. An example of a six-transistor memory cell memory cell
10
is shown in FIG.
1
. Such a memory cell is useful for static memory arrays such as, for example, cache memories, first-in-first-out buffers (FIFOs) and stand-alone static random access memories (SRAMs). The memory cell
10
includes a pair of cross-coupled N-channel transistors
15
,
16
coupling a complementary pair of internal nodes
17
,
18
to ground. A pair of cross-coupled P-channel transistors
13
,
14
couple the internal nodes
17
,
18
to an upper power supply voltage, such as VDD. As shown in
FIG. 1
, an isolated array power supply VDDMX (i.e., “VDD matrix”) may be employed which is separate from the VDD used in other sections of an integrated circuit containing such an array of memory cells. Together, the pair of cross-coupled N-channel transistors
15
,
16
and the pair of cross-coupled P-channel transistors
13
,
14
form a static flip-flop, which is read and written by way of two N-channel access transistors
11
,
12
which respectively couple internal nodes
17
,
18
to true and complement bit lines
19
,
20
when its word line
21
is selected and driven high.
One of the challenges in making a small SRAM cell is that of cell stability. That is, it must be possible to read the data from the cell without disturbing the data stored in the cell. One of the critical factors in determining cell stability is often referred to as the “Beta” ratio. This is generally thought of as the conductance ratio of the pulldown transistors (transistors
15
and
16
) to that of the access transistors (transistors
11
and
12
). For the transistor sizing shown in
FIG. 1
, such a Beta ratio is equal to [(W/L of pulldown transistor)÷(W/L of access transistor)]=[(1.0/0.4)÷(0.7/0.4)]=1.43. The larger the Beta ratio (large pulldown transistors and small access transistors) the more stable the cell.
An additional factor which is crucial to the cell stability is any difference in channel length between the pulldown transistors (transistors
15
and
16
), the P-channel pullup transistors (transistors
13
and
14
), or the access transistors (transistors
11
and
12
). The memory cells at the very edge of an array are susceptible to such variation in channel length due to the lithographic proximity effects already noted. In effect, the transistors on the outside edge of the outermost memory cells (both the last row and the last column of the array) will have gate lengths (as well as other attributes) that are different than the transistors on the inside edge of these cells. These effects contribute to a degradation of the cell stability because the variations in channel length (and other attributes) induce differential offsets in the cell.
To reduce these undesirable edge effects, it is common to add non-functional sacrificial rows and columns of otherwise identical or nearly identical memory cells around the periphery of a memory array. The “word lines” of such sacrificial rows of memory cells are frequently grounded (i.e., connected to the lower power supply, VSS), and the “bit lines” of such sacrificial columns of memory cells are frequently connected to the upper power supply (e.g., VDD). By adding these sacrificial cells, all of the data-storing cells in the array (including those at the edges of the array) are contained in a lithographically homogeneous environment. Consequently, variations in channel length and other attributes are reduced, and memory cell stability is enhanced. However, these sacrificial “guard” cells add to the array area without increasing the storage capacity of the array. Improved techniques for reducing these memory array edge effects are desirable.
SUMMARY OF THE INVENTION
To save area, a group of functional memory cells in one array may also be used as guard cells for another memory array. The memory cells of the one array may, for example, be redundant memory cells serving the other memory array. In one embodiment having several memory submodules or banks, an array of four redundant rows is placed adjacent to the array of one of the memory banks. Separate sacrificial guard cells for the adjoining edge of the one memory bank are therefore no longer needed, and the area consumed by such guard cells is eliminated. In another embodiment, a portion of a functional array also services as guard cells for the remaining portion of the array. In each case, all masking layers which together define the transistors within the memory cells are identical between the functional cells which also serve as guard cells and the regular array memory cells. Thus, the lithographic environment at the edge of the regular rows, for at least the lower masking layers, is homogeneous with the environment anywhere in the middle of the array of regular memory cells. By abutting the redundant and normal memory cell arrays in this matter, we have eliminated the need for sacrificial guard cells (or “edge cells” or “end cells”) for both arrays along their adjoining edges, saving both layout area and layout complexity. In other embodiments, redundant columns may also serve as guard cells.
In one embodiment of the invention, a semiconductor integrated circuit includes a first functional array of memory cells, and a second functional array of memory cells positioned adjacent to one edge of the first array. The memory cells of the second array also serve as guard cells for the memory cells of the first array along the one edge of the first array. The integrated circuit may include a plurality of guard cells adjacent to at least one of three remaining edges of the first memory array. The memory cells of the second array may be stepped to form, for at least a subset of lithographic layers of the semiconductor process, an unbroken homogeneous lithographic array with the memory cells of the first array. The subset of lithographic layers may include layers which together define transistors within the memory cells, may include at least one polysilicon layer and at least one active area layer, and may include all layers below and including a first metal layer. In some embodiments, the second array may provide redundant memory cells organized as redundant rows for the first array. The second array may share local bit lines in common with the first array, or may include local bit lines which are disjoint from local bit lines within the first array. Bit line circuits for the local bit lines within the first array may be located on an opposite side of the collective first and second arrays as bit line circuits for the local bit lines within the second array.
In another embodiment of the invention, a semiconductor integrated circuit includes an array of memory cells surrounded on three sides by guard cells. A group of addressable memory cells located along a fourth side of the array function as guard cells for remaining memory cells of the array. The group of addressable memory cells may be organized as redundant rows for the remainder of the array, and may share bit lines in common with the remainder of the array, or may include bit lines which are disjoint from bit lines within the remainder of the array. Bit line circuits for the bit lines serving the group of addressable memory cells may be located on an opposite side of the array as bit line circuits serving the remaining memory cells of the array. The group of addressable

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