Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2003-01-22
2004-11-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S289000, C438S514000, C438S516000, C438S770000, C438S775000, C438S776000, C438S778000
Reexamination Certificate
active
06825133
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form a charge balanced, nitrided gate dielectric layer for a metal oxide semiconductor field effect transistor (MOSFET), device.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, have allowed performance increases for the sub-micron MOSFET devices to be realized, basically via reductions in performance degrading junction capacitances. Sub-micron MOSFET devices are also being fabricating featuring thin silicon dioxide gate insulator layers, used to allow operating voltages to be decreased. However the thinner silicon dioxide layers can present higher leakage currents than counterparts comprised with thicker silicon dioxide gate insulator layers. Subjecting the thin silicon dioxide gate insulator layers to a plasma nitrogen procedure, or to an anneal in a nitrogen containing ambient, can reduce leakage in the thin silicon dioxide layers, however at risk of inducing positive charge in the thin silicon dioxide gate insulator layer. The effect of the positive charge, generated in the silicon dioxide layer as a result of nitriding, is a negative flatband voltage (V
fb
) shift for silicon dioxide gate insulator layers employed in both N channel metal oxide semiconductor (NMOS), as well as in P channel metal oxide semiconductor (PMOS) devices. The negative V
fb
shift directly correlates to negative shifts for the threshold voltage (Vt) of these devices, making V
t
adjust implantation procedures difficult to control. In addition the negative V
fb
shift is more pronounced in PMOS devices, making the PMOS Vt adjust implantation procedure even more difficult to target.
This invention will describe a procedure in which a silicon dioxide gate insulator layer is prepared, comprised with negative charge. Subsequent nitridization procedures introducing positive charge now result in a balancing, or neutralization of charges, allowing the leakage of thin silicon dioxide layers used as gate insulator layers for MOSFET devices, to be reduced without the risk of negative V
t
shifts. Prior art such as. Sun et al, in U.S. Pat. No. 6,258,730 B1; Lu et al, in U.S. Pat. No. 5,683,946; Klingbeil, Jr. et al, in U.S. Pat. No. 5,882,961; Ngaoaram, in U.S. Pat. No. 5,714,788; Mitani et al, in U.S. Pat. No. 6,191,463; and Akran et al, in U.S. Pat. No. 6,288,433 B1; describe methods for nitriding silicon dioxide layers, or implanting fluorine into silicon dioxide gate insulator layers, however these prior art do not describe the unique combination of process steps, described in this present invention, in which charge balancing, or charge neutralization in the silicon dioxide gate insulator layer is achieved.
SUMMARY OF THE INVENTION
It is an object of this invention to form charge balanced silicon dioxide gate insulator layers, for both PMOS and NMOS devices.
It is another object of this invention to implant fluorine ions into a region of a silicon substrate prior to formation of a thermally grown silicon dioxide gate insulator layer, followed by the thermal oxidation procedure resulting in the incorporation of fluorine ions, and negative charge, in the thermally grown silicon dioxide layer.
It is still another object of this invention to subject the silicon dioxide layer comprised with negative charge to a nitridization procedure, resulting in the incorporation of positive charge in the underlying silicon dioxide layer which in turn neutralizes the previously generated negative charge in the now charge balanced silicon dioxide gate insulator layer.
In accordance with the present invention a method of forming a charge balanced, thin silicon dioxide gate insulator layer, in which leakage current is minimized via a nitridization procedure, and the charge in the gate insulator layer is balanced via incorporation of fluorine ions into the silicon dioxide layer during thermal oxidation, is described. After formation of a silicon oxide screen insulator layer on a semiconductor substrate, fluorine ions are implanted into a top portion of the semiconductor substrate. After removal of the screen insulator layer a silicon dioxide gate insulator layer is thermally grown consuming a top portion of the semiconductor substrate with incorporation of the implanted fluorine ions, allowing a negative charge in the thermally grown silicon dioxide layer to be achieved. The procedure for reducing gate insulator leakage such as: a plasma nitridization procedure; an anneal in a nitrogen ambient such as NO/N
2
O/NH
3
; or deposition of an overlying silicon nitride layer; is then employed also resulting in the generation of positive charge in the underlying silicon dioxide gate insulator layer, with the negative charge delivered via the incorporated fluorine ions, balanced by the positive charge created by the nitridization procedure, thus resulting in a charge balanced silicon dioxide gate insulator layer, featuring low leakage currents.
REFERENCES:
patent: 5571734 (1996-11-01), Tseng et al.
patent: 5683946 (1997-11-01), Lu et al.
patent: 5714788 (1998-02-01), Ngaoaram
patent: 5882961 (1999-03-01), Klingbeil, Jr. et al.
patent: 6191463 (2001-02-01), Mitani et al.
patent: 6258730 (2001-07-01), Sun et al.
patent: 6288433 (2001-09-01), Akram et al.
patent: 6432786 (2002-08-01), Chen et al.
Lin Shyue-Shyh
Yu Mo-Chiun
Elms Richard
Haynes and Boone LLP
Owens Beth E.
Taiwan Semiconductor Manufacturing Company , Ltd.
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