Use of discrete conductive layer in semiconductor device to...

Details Use of discrete conductive layer in semiconductor device to... Use of discrete conductive layer in semiconductor device to...

2011-01-14

2011-11-01

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S780000, C257S781000, C257S784000, C257SE23010, C257SE23058

Reexamination Certificate

active

08049315

ABSTRACT:
A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

REFERENCES:
patent: 5495398 (1996-02-01), Takiar et al.
patent: 5557842 (1996-09-01), Bailey
patent: 5814884 (1998-09-01), Davis et al.
patent: 5917241 (1999-06-01), Nakayama et al.
patent: 6031279 (2000-02-01), Lenz
patent: 6055148 (2000-04-01), Grover
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6249041 (2001-06-01), Kasem et al.
patent: 6265763 (2001-07-01), Jao et al.
patent: 6414387 (2002-07-01), Hara et al.
patent: 6424035 (2002-07-01), Sapp et al.
patent: 6593622 (2003-07-01), Kinzer et al.
patent: 6677669 (2004-01-01), Standing
patent: 6777800 (2004-08-01), Madrid et al.
patent: 6841852 (2005-01-01), Luo et al.
patent: 6858922 (2005-02-01), Pavier
patent: 6864588 (2005-03-01), Hung
patent: 6933593 (2005-08-01), Fissore et al.
patent: 7030501 (2006-04-01), Yoshiba et al.
patent: 7057273 (2006-06-01), Harnden et al.
patent: 7088074 (2006-08-01), Clevenger et al.
patent: 7115985 (2006-10-01), Antol et al.
patent: 7166496 (2007-01-01), Lopez et al.
patent: 7166919 (2007-01-01), Tabira
patent: 7183616 (2007-02-01), Bhalla et al.
patent: 7215012 (2007-05-01), Harnden et al.
patent: 7301235 (2007-11-01), Schaffer et al.
patent: 7508012 (2009-03-01), Otremba
patent: 7511361 (2009-03-01), Zhang et al.
patent: 7514778 (2009-04-01), Otremba et al.
patent: 7612439 (2009-11-01), Zhang et al.
patent: 2001/0019490 (2001-09-01), Igarashi et al.
patent: 2002/0093094 (2002-07-01), Takagawa et al.
patent: 2002/0163040 (2002-11-01), Kinzer et al.
patent: 2004/0004272 (2004-01-01), Luo et al.
patent: 2004/0227547 (2004-11-01), Shiraishi et al.
patent: 2004/0251529 (2004-12-01), Lee et al.
patent: 2005/0017339 (2005-01-01), Yoshiba et al.
patent: 2005/0082679 (2005-04-01), Otremba
patent: 2005/0133902 (2005-06-01), Pavier et al.
patent: 2005/0145996 (2005-07-01), Luo et al.
patent: 2005/0145998 (2005-07-01), Harnden et al.
patent: 2006/0118815 (2006-06-01), Otremba et al.
patent: 2006/0145312 (2006-07-01), Liu
patent: 2006/0145318 (2006-07-01), Zhang et al.
patent: 2007/0007640 (2007-01-01), Harnden et al.
patent: 2007/0080443 (2007-04-01), Sun et al.
patent: 2007/0085187 (2007-04-01), Sun et al.
patent: 2007/0145609 (2007-06-01), Zhang et al.
patent: 2007/0215996 (2007-09-01), Otremba
patent: 2008/0111219 (2008-05-01), Harnden et al.
patent: 2008/0207094 (2008-08-01), Feng et al.
patent: 2008/0224323 (2008-09-01), Otremba
patent: 2008/0242052 (2008-10-01), Feng et al.
patent: 2008/0296782 (2008-12-01), Otremba et al.
patent: 2009/0008758 (2009-01-01), Lu et al.
patent: 2009/0020854 (2009-01-01), Feng et al.
patent: 2009/0128968 (2009-05-01), Lu et al.
patent: 2009/0179265 (2009-07-01), Harnden et al.
patent: 2009/0189281 (2009-07-01), Han
patent: 2009/0258458 (2009-10-01), Zhang et al.
patent: 10-0826989 (2004-11-01), None
patent: 10-2004-92304 (2008-05-01), None
patent: 375330 (1999-11-01), None
Notice of Allowance and Fees Due dated Oct. 1, 2010 issued for U.S. Appl. No. 11/944,313.
Notice of Rejection dated Nov. 16, 2010 issued for Korean patent application No. 10-2009-0019811.
International Search Report and Written Opinion of the International Searching Authority dated Apr. 6, 2009 for the International Patent Application No. PCT/US2008/074924, 11 pages.
Office Action dated Nov. 24, 2009 for U.S. Appl. No. 11/944,313.
Ex Parter Quayle Action dated Nov. 25, 2008 for U.S. Appl. No. 11/316,614.
Notice of Allowance and Fee(s) Due dated Jun. 25, 2009 for U.S. Appl. No. 11/316,614.
Office Action dated May 16, 2007 for U.S. Appl. No. 11/150,489.
Notice of Allowance and Fee(s) Due dated Nov. 17, 2008 for U.S. Appl. No. 11/150,489.
Final Office Action dated Feb. 25, 2008 for U.S. Appl. No. 11/150,489.
Final Office Action dated Feb. 23, 2010 for U.S. Appl. No. 11/029,653.
International Search Report and Written Opinion of International Application No. PCT/US06/00356, mailing date Jul. 19, 2006.
Notification concerning availability of the publication of the International Application of PCT/US06/00356, mailing date Nov. 9, 2006.
Notification concerning transmittal of international preliminary report for PCT/US06/00356, mailing date Jul. 19, 2007.
International Search Report and Written Opinion of International Application No. PCT/US2006/022909 mailing date Feb. 28, 2008.
Notification Concerning Transmittal of international Preliminary Report on Patentability for PCT/US2006/022909, Mailing date Mar. 19, 2009.
Office Action dated Aug. 18, 2009 for U.S. Appl. No. 11/029,653.
U.S. Appl. No. 12/384,100, filed Mar. 30, 2009, entitled DFN Semiconductor Package Having Reduced Electrical Resistence and identifying Xiaotian Zhang et al. as inventors.
English translation of Taiwanese model No. 375330 published Nov. 21, 1999.
Notice of Allowance and Fee(s) Due dated Sep. 17, 2008 for U.S. Appl. No. 11/029,653.
Office Action dated Mar. 20, 2008 for U.S. Appl. No. 11/029,653.
General definition of Dual Flat No lead by www.answers.com search word: Dual flat no lead.
Advisory Action dated Nov. 27, 2007 for U.S. Appl. No. 11/029,653.
Final Office Action dated Aug. 6, 2007 for U.S. Appl. No. 11/029,653.
Office Action dated Nov. 28, 2006 for U.S. Appl. No. 11/029,653.
Office Action dated Feb. 22, 2006 issued for U.S. Appl. No. 11/029,653.
Office Action dated Apr. 14, 2010 issued for U.S. Appl. No. 11/944,313.
Advisory Action dated Jul. 28, 2008 issued for U.S. Appl. No. 11/150,489.
Notice of Allowance and Fees Due dated Jun. 23, 2008 issued for U.S. Appl. No. 11/316,614.
Office Action dated Feb. 6, 2008 issued for U.S. Appl. No. 11/316,614.
Bonnie C. Baker, “Smaller Packages = Bigger Thermal Challenges”, 2003 Microchip Technology, Inc.
Office Action dated Apr. 14, 2010 issued for U.S. Appl. No. 12/209,106.
Notice of Allowance and Fee(s) Due dated Sep. 30, 2010 issued for U.S. Appl. No. 12/209,106.

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