Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-02
2001-07-10
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S639000, C438S672000, C438S723000, C438S757000
Reexamination Certificate
active
06258678
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to precesses used to fabricate semiconductor devices, and more specifically to a process used to create a self-aligned contact, (SAC), structure, for a semiconductor device.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase the performance of semiconductor chips, while still attempting to decrease the manufacturing cost of these same, higher performing, semiconductor chips. The advent of micro-miniaturization, or the creation of semiconductor chips comprised with sub-micron features, have allowed these performance and cost objectives to be partially realized. The use of sub-micron features have resulted in decreases in performance degrading, junction capacitances, allowing the desired performance enhancements to be realized. In addition the use of sub-micron features allow smaller semiconductor chips, still containing device densities, equal, or greater to device densities achieved with larger semiconductor chips, to be realized. The attainment of the smaller semiconductor chip allows a greater number of chips to be obtained from a specific size starting substrate, thus reducing the processing cost of a specific semiconductor chip.
Advances in specific semiconductor disciplines, such as photolithography, and dry etching, have been major contributors to micro-miniaturization, however structural innovations, such as the use of self-aligned contact, (SAC), openings, and SAC structures, have also played a vital role in achieving the performance and cost objectives of the semiconductor industry. The use of SAC opening, allows a conductive structure, to be fully landed on an underlying active device region. For example if a design called for a metal structure to be fully landed on a source/drain region, of a metal oxide semiconductor field effect transistor, (MOSFET), device, the area of the source/drain region would have to be designed large enough to accommodate any possible misalignment of the contact or via hole, used to accommodate the fully landed metal structure, to the underlying source/drain region. The use of this additional real estate, increases the size of the semiconductor chip. The SAC opening, in an insulator layer, however is formed between silicon nitride capped, gate structures, exposing a source/drain region located between the silicon nitride gate structures. Therefore the SAC opening, formed between gate structures, and accomplished via a high etch rate ratio of silicon oxide to silicon nitride, is designed with a diameter larger than the space between the silicon nitride capped, gate structures, thus insuring fully landed SAC structures, to underlying source/drain regions. This in turn allows designers to use a smaller area for the source/drain region, guarantying fully landed SAC structures, thus allowing smaller semiconductor chips to be obtained.
The procedure for creating a SAC opening, in an insulator layer such as silicon oxide, is dependent on the selectivity, or etch rate ratio, of silicon oxide to silicon nitride. A thin layer of silicon nitride is therefore used as an etch stop during the formation of the first phase of SAC opening, in the silicon oxide layer, preventing attack of the active device region, after complete removal of the silicon oxide component. However the selectivity of silicon oxide to silicon nitride, is obtained via the formation of a polymer layer, on the surface of the thin silicon nitride layer, exposed at the conclusion of the silicon oxide etch cycle. If this polymer layer is not effectively removed, subsequent removal of the thin silicon nitride layer can not be adequately accomplished, resulting in unwanted resistance between a subsequent SAC structure, and the underlying source/drain region. This invention will describe a SAC opening procedure, featuring a wet etch cycle, used to insure complete removal of the polymer layer, formed on the thin silicon nitride layer during the SAC opening formation. Prior art, such as Lee et al, in U.S. Pat. No. 5,865,900, describe a procedure in which a series of dry etch cycles are used to remove polymer from surfaces of a silicon oxide layer, with the polymer formed during a metal patterning procedure. That prior art however does not teach the wet etch cycle, featured in this invention, and used as apart of SAC opening procedure, removing polymer from the surface of a thin silicon nitride etch stop layer.
SUMMARY OF THE INVENTION
It is an object of this invention to form a self-aligned contact, (SAC), structure, in SAC opening, to overlay and contact, a MOSFET active device region, located in a semiconductor substrate.
It is another object of this invention to perform a first phase of the SAC opening procedure, in a silicon oxide layer, via a selective dry etching procedure, using a thin underlying silicon nitride layer, as an etch stop.
It is still another object of this invention, to perform a second phase of the SAC opening procedure, to remove polymer formed on the surface of the thin silicon nitride layer at the conclusion the first phase of the SAC opening, using a wet etch procedure.
It is still yet another object of this invention to perform a third phase of the SAC opening procedure, to remove exposed regions of the thin silicon nitride layer.
In accordance with the present invention a method of forming a SAC structure, in a SAC opening, wherein the SAC opening procedure features the use of a wet etch cycle, used to remove polymer formed on an underlying silicon nitride layer, used as an etch stop during the formation of the SAC opening in an overlying silicon oxide layer, is described. After formation of silicon nitride capped gate structures, on an underlying gate insulator layer, a lightly doped source/drain region is formed in a region of the semiconductor substrate, located between, and not covered by, the silicon nitride capped gate structures. After formation of a thin silicon oxide layer, on the exposed surfaces of the silicon nitride capped gate structures, and on the surface of the lightly doped source/drain region, silicon nitride spacers are formed on the sides of the silicon nitride capped gate structures, followed by the formation of a heavily doped source/drain region, in an area of the semiconductor substrate, not covered by the silicon nitride capped gate structure or by the silicon nitride spacers. A thin silicon nitride layer, and a thick silicon oxide, interlevel dielectric layer, (ILD), are next deposited, followed by the formation of a SAC opening, in the ILD layer, selectively formed via a dry etching cycle, terminating at the appearance of the thin silicon nitride layer, and at the appearance of a polymer deposit, formed on the top surface of the thin silicon nitride layer. A wet etch cycle is next used to selectively remove polymer deposit from the surface of the thin silicon nitride layer. A final phase of the SAC opening is then performed, removing regions of the thin silicon nitride layer, exposed in the SAC opening. After a wet etch dip, used to remove the thin silicon oxide layer, residing on the surface of the heavily doped source/drain region, a SAC structure, is formed in the SAC opening, overlying and contacting, the top surface of the heavily doped source/drain region, located at the bottom of the SAC opening.
REFERENCES:
patent: 4837176 (1989-06-01), Zdebel et al.
patent: 4997790 (1991-03-01), Woo et al.
patent: 5219793 (1993-06-01), Cooper et al.
patent: 5431778 (1995-07-01), Dahm et al.
patent: 5597983 (1997-01-01), Nguyen et al.
patent: 5731236 (1998-03-01), Chou et al.
patent: 5744024 (1998-04-01), Fukazawa et al.
patent: 5804506 (1998-09-01), Haller et al.
patent: 5865900 (1999-02-01), Lee et al.
patent: 5880019 (1999-03-01), Hsieh et al.
patent: 6057581 (2000-05-01), Doan
patent: 6077776 (2000-06-01), Cho et al.
patent: 6093641 (2000-07-01), Park
patent: 6110792 (2000-08-01), Bronner et al.
patent: 6136658 (2000-10-01), Shinmura
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6174774 (2001-01-01), Lee
Wolf
Ackerman Stephen B.
Fahmy Wael
Saile George O.
Taiwan Semiconductor Manufacturing Company
Toledo Fernando
LandOfFree
Use of a wet etch dip step used as part of a self-aligned... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of a wet etch dip step used as part of a self-aligned..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of a wet etch dip step used as part of a self-aligned... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2501937