Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-02-22
2011-02-22
Sarkar, Asok K (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21431, C257SE21437, C257SE21632, C438S199000
Reexamination Certificate
active
07892931
ABSTRACT:
A method300for forming a transistor's drain extension70and recessed strained epi regions150with a single mask step306. In an example embodiment, the method300may include forming a patterned photoresist layer200over a protection layer190in a NMOS region50and then etching exposed portions of the protection layer190in the PMOS region60to form extension sidewalls210on the transistors30in the PMOS region60plus a protective hardmask220over the NMOS region50. The method300may further include forming the extension regions70for the PMOS region transistors30, performing a recess etch240of active regions230of the PMOS region transistors30, and forming the recessed strained epi regions150.
REFERENCES:
patent: 6544874 (2003-04-01), Mandelman et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6642125 (2003-11-01), Oh et al.
patent: 6900502 (2005-05-01), Ge et al.
patent: 7112495 (2006-09-01), Ko et al.
patent: 7176481 (2007-02-01), Chen et al.
patent: 7282415 (2007-10-01), Zhang et al.
patent: 2004/0262694 (2004-12-01), Chidambaram et al.
patent: 2005/0035409 (2005-02-01), Ko et al.
patent: 2005/0090082 (2005-04-01), Sridhar et al.
patent: 2005/0139872 (2005-06-01), Chidambaram et al.
patent: 2006/0022266 (2006-02-01), Messenger et al.
patent: 2006/0046367 (2006-03-01), Rotondaro et al.
patent: 2006/0240636 (2006-10-01), Ryu et al.
patent: 2007/0020839 (2007-01-01), Sridhar et al.
patent: 2007/0296038 (2007-12-01), Chen et al.
Mansoori Majid
Sridhar Seetharaman
Brady III Wade J.
Keagy Rose Alyssa
Sarkar Asok K
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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