Use of a rapid thermal anneal process to control drive current

Details Use of a rapid thermal anneal process to control drive current Use of a rapid thermal anneal process to control drive current

1999-10-25

2001-07-10

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S303000, C438S307000, C438S530000, C438S542000

Reexamination Certificate

active

06258681

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to using a rapid thermal anneal process to control the drive current of a transistor.
2. Description of the Related Art
By way of background,
FIG. 1
depicts an illustrative NMOS field effect transistor
10
formed above a surface
14
of a semiconducting substrate
12
between trench isolation regions
25
. The transistor
10
is comprised of a gate dielectric
16
, a gate conductor
18
, a plurality of sidewall spacers
20
and source/drain regions
28
.
In the design of modem transistors, a parameter known as drive current (I
D
) is a significant parameter. In general, the drive current is the amount of current flowing through a transistor when it is turned “ON”, i.e., when the proper voltage is applied to the gate conductor
18
of the transistor
10
. However, the drive current of a transistor is affected by the physical dimensions of a transistor or some of its components, e.g., the nominal channel length “L”, which is roughly equivalent to the width of the gate conductor
18
, the width of the sidewall spacers
20
, and the thickness of the gate dielectric
16
, etc. For example, all the other things being equal, the larger the channel length, the slower the transistor will operate. Similarly, the thicker the gate dielectric, the slower the transistor will operate.
During the course of manufacturing a transistor, the size of the various components of the transistor, as actually built, may vary from the anticipated or design size of the components. As a result, transistor performance, as well as integrated circuit devices incorporating such transistors, may be adversely impacted. For example, assume that a gate conductor
18
is formed to a width greater that its design width, this will result in the channel length of the transistor being greater that anticipated. As a result, the transistor will operate at a slower speed. When this occurs to many of the thousands of transistors formed on an integrated circuit device, the overall operating speed and efficiency of the integrated circuit device may also suffer. What is desired is to have a method for manufacturing transistors, and integrated circuit devices incorporating the same, that helps to maintain device performance within acceptable limits. In particular, it is desirable to have a method of compensating for variations in the manufacturing process that may adversely impact the drive current of the transistor.
The present invention is directed to a method of making a semiconductor device that minimizes or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to the use of an anneal process to improve or control the performance of a semiconductor device, e.g., a transistor, as well as integrated circuit products incorporating such devices. In on illustrative embodiment, the method initially comprises determining a size variation of a component of a transistor, e.g., the width of the gate conductor, the width of a sidewall spacer or the thickness of the gate dielectric, etc., as compared to the design size of that component. Thereafter, the method comprises determining at least one parameter of an anneal process to be performed on the transistor based upon the determined size variation of the component, and performing the determined anneal process. In another illustrative embodiment, the method comprises determining a physical dimension of a gate conductor, a sidewall spacer or a gate dielectric of a transistor, determining at least one parameter of an anneal process to be performed on the transistor based upon the determined physical dimension, and performing the determined anneal process.


REFERENCES:
patent: 5960283 (1999-09-01), Sato
patent: 6051483 (2000-04-01), Lee et al.

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