Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-07
1998-10-06
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438255, 438398, H01L 218242
Patent
active
058175547
ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a grated, top surface topography, in a polysilicon layer, that is used for polysilicon storage node electrode formation. The grated, top surface topography is obtained by anisotropic etching of the polysilicon layer, exposed between masking silicon oxide spots. The silicon oxide spots had been obtained via oxidation of small diameter, HSG polysilicon spots. The resulting grated, top surface topography, is comprised of raised, unetched features, and lower, etched features, in the polysilicon layer, used for the storage node electrode, increasing capacitor surface area, and thus increasing DRAM capacitance.
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Watanabe et al, "Hemispherical Gran Silicon for High Density DRAMs", Solid State Technology, Jul. 1992, pp. 29-33.
Ackerman Stephen B.
Chang Joni
Saile George O.
Vanguard International Semiconductor Corporation
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