UPROM cell for low voltage supply

Static information storage and retrieval – Read/write circuit – Precharge

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Details

36518905, 36518907, G11C 700

Patent

active

058222596

ABSTRACT:
The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the memory element with a reference low voltage power supply. There is provided a precharge network for the conduction terminal of the flash cell and the network incorporates a complementary pair of transistors. The second transistor of the pair is a natural N-channel MOS type. With the UPROM cell is associated a circuit portion for generating a second live output signal to be applied to the control terminal of the second transistor. The circuit portion includes a timing section and a generation section for the second live output signal.

REFERENCES:
patent: 5357458 (1994-10-01), Yu et al.
patent: 5592416 (1997-01-01), Bonitz et al.
patent: 5606523 (1997-02-01), Mirabel
patent: 5671186 (1997-09-01), Igura

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