Unit cell layout and transfer gate design for high density DRAMs

Details Unit cell layout and transfer gate design for high density DRAMs Unit cell layout and transfer gate design for high density DRAMs

1996-07-15

1999-12-21

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438389, H01L 218242

Patent

active

060048441

ABSTRACT:
A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.

REFERENCES:
patent: 5389559 (1995-02-01), Hsieh et al.

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