Uniformly doped source/drain junction in a double-gate MOSFET

Details Uniformly doped source/drain junction in a double-gate MOSFET Uniformly doped source/drain junction in a double-gate MOSFET

2003-03-12

2004-04-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S149000, C438S151000, C438S230000, C438S231000, C438S232000, C438S303000, C438S311000, C438S479000, C438S495000, C438S514000, C438S519000, C438S682000, C438S914000

Reexamination Certificate

active

06716690

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to semiconductor manufacturing and semiconductor devices and, more particularly, to double gate metal-oxide semiconductor field-effect transistors (MOSFETs).
B. Description of Related Art
Transistors, such as MOSFETs, are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processors, can include millions of transistors. For these devices, decreasing transistor size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing area.
Conventional MOSFETs have difficulty scaling below 50 nm fabrication processing. To develop sub-50 nm MOSFETs, double-gate MOSFETs have been proposed. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
A FinFET, as the term is used herein, refers to a type of double-gate MOSFET in which a conducting channel is formed in a vertical Si “fin” controlled by a self-aligned double-gate. FinFETs are known in the art. FinFETs tend to scale well to small device dimensions and may thus be desirable when designing semiconductor integrated circuits.
SUMMARY OF THE INVENTION
Implementations consistent with the present invention include a FinFET having vertically uniform dopant concentrations in the source/drain junction, and methods of manufacturing the same.
One aspect of the invention is directed to a method for forming a MOSFET. The method includes forming a source, a drain, and a fin structure on an insulating layer, portions of the fin structure acting as a channel for the MOSFET. The method further includes performing a first implantation with a first dopant of the source and the drain; and performing a second implantation with the first dopant of the source and the drain, the second implantation being performed at a tilt angle different than a tilt angle of the first implantation.
In another implementation consistent with principles of the invention, a method includes forming a source, a drain, and a fin structure on an insulating layer, portions of the fin structure acting as a channel for the MOSFET. The method further includes implanting the source and the drain with a first dopant using a number of implantation steps in which each of the implantation steps is performed at different tilt angles, wherein the implantation steps cause a concentration of the first dopant to be substantially uniform along a vertical depth of a junction of the source and the drain.


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