Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-09-30
2001-01-09
Dinh, Son T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06172915
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to floating gate memory devices such as an array of flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to a unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector (entire array) erasing operation with a reduced amount of total erase time.
As is generally well-known in the art, there have been provided electrical programmable and erasable memory array devices using a floating gate for the storage of charges thereon. In a conventional EEPROM memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
A particular type of EEPROM referred to sometimes as a “flash EPROM or EEPROM” divides the memory cells into a plurality of sectors. Within each sector, the source region of each cell transistor is tied to a common node. Therefore, all of the cells within the sector are erased simultaneously and erasure is performed only on a sector-by-sector basis. The control gates of the cell transistors are coupled to wordlines, and the drains thereof are coupled to bitlines.
Such EEPROMs are programmed in a conventional operation via hot-electron injection to the floating gate by application of high voltages to the control gate and the drain region which are above the potential applied to the source region. For example, the drain voltage applied is approximately +5.5 volts and the control gate voltage is approximately +12 volts. The source region is held at a ground potential. For the erasing operation by way of Fowler-Norheim tunneling, a positive voltage (e.g., +5 volts) is applied to the source region. A negative voltage (e.g., −8 volts) is applied to the control gate, and the drain region is allowed to float. In a read operation, the source region is held at a ground potential (0 volts) and the control gate has applied thereto a voltage of about +5 volts. The drain region is held at a voltage between +1 to +2 volts. Under these conditions, an unprogrammed or erased cell (storing a logic “1”) will conduct a predetermined amount of current. On the other hand, the programmed cell (storing a logic “0”) will not be rendered conductive. It should be clearly understood that the above examples are given for explanation only and that other voltage values may be used so as to provide similar programming, erasing, and reading operations.
For instance, a 4 Mb (megabit) flash memory core array is typically manufactured in the form of an N×M matrix on a single chip where N equals the number of rows and M equals the number of columns. The array is divided into a number of sectors, such as eight, each sector defining a selectable block. Each sector is formed of a predetermined number of rows which are grouped together. For the 4 Mb array divided into eight sectors, each block has a size of 512 K bits or 64 K bytes and may consist of 512 rows and 128 byte columns. Such a typical 4 Mb array
10
is shown in
FIG. 1
which is composed of sector ∅ through sector 7 corresponding to blocks
12
,
14
,
16
,
18
,
20
,
22
,
24
and
26
. Each of the sectors or blocks
12
-
26
stores 512 K bits of data arranged in 512 rows and 128 byte columns.
In conventional operation, the data stored in each of the plurality of sectors or blocks
12
-
26
can be altered independently. In other words, data stored in certain ones of the sectors can be changed while the data stored in the other remaining sectors are kept unchanged. In order to alter the storage content in one of the plurality of sectors such as sector ∅ (block
12
), a sector-erase command is first executed. After the sector-erase command has been issued, this will cause the data pattern stored in the sector ∅ to have all logic “1” pattern. Then, sector ∅ is ready to have re-written into it whatever new data pattern is desired by the user.
In other cases, it will be needed that the storage content (data pattern) in all of the sectors, sector ∅ through sector 7 (entire array or chip), be altered. As a result, instead of generating the sector-erase command, a chip-erase command will be executed. After the chip-erase command has been issued, this will cause the data pattern stored in all of the sectors, sector ∅ through sector 7, to have all logic “1” pattern. Thereafter, all of the sectors (∅-7) are ready to have re-written into them whatever new data patterns are desired by the user.
Unfortunately, the chip-erase command is merely a sequence of sector-erase commands consisting of a first erase-sector command for sector ∅, a second erase-sector command for sector 1, . . . an eighth erase-sector command for sector 7. Thus, the total erase time in the chip-erase operation is the summation of the erase times for all of the eight sectors. In other words, the chip-erase time is approximately 8 times as long as the sector-erase time for one sector. Therefore, the chip-erase operation is still a time-consuming task utilizing this sequential approach.
Accordingly, it would be desirable to provide an improved erase method for performing an erasing operation with a reduced amount of total erase time, while maintaining the threshold voltage V
T
distribution after a multiple-sector or all-sector erasing operation to be as good as the V
T
distribution after a conventional single-sector erase operation.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved erasing method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing an erasing operation with a reduced amount of total erase time than has been traditionally available.
It is an object of the present invention to provide a unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time.
It is another object of the present invention to provide a unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors which applies an erase pulse to all sectors simultaneously in which the erase-on signals have not been turned off.
It is still another object of the present invention to provide an improved erasing method used in an array of flash EEPROM memory cells arranged in a plurality of sectors which stores the current address of each sector in a corresponding register at a point where an erase-verify operation fails and applies an erase pulse simultaneously and only to all sectors that have not passed the erase-verify operation.
In a preferred embodiment of the present invention, there is provided an unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time. An erase-on signal is turned ON only in certain ones of the plurality of sectors which are required to be erased. All bytes in the certain ones of the plurality of sectors which are required to be erased are programmed to all “0” state initially. The current address in the certain ones of the plurality of sectors which are required to be erased are set to a first address. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector
Anthony Jeffrey W.
Tang Yuan
Yu James C.
Chin Davis
Dinh Son T.
EON Silicon Devices, Inc.
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