Underfill preform interposer for joining chip to substrate

Details Underfill preform interposer for joining chip to substrate Underfill preform interposer for joining chip to substrate

1999-01-19

2001-07-10

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S106000, C438S118000

Reexamination Certificate

active

06258627

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Aspects of the present invention are related to subject matter disclosed in co-pending applications entitled “Process for Forming Cone Shaped Solder for Chip Interconnection,” Attorney Docket No. FI9-97-060, and “Dielectric Interposer for Chip to Substrate Soldering,” Attorney Docket No. FI9-98-129 filed on even date herewith and assigned to the assignee of the present invention.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the assembly of electronic modules, and in particular, to a structure and method of minimizing the thermo-mechanical fatigue that typically occurs as a result of the mismatch in the coefficients of thermal expansion of a chip and a substrate when they are joined in a flip-chip arrangement. It has wide applicability, including extension to very small joints and very densely populated arrays.
2. Description of Related Art
Multi-layer ceramic electronic components are typically joined together by soldering pads on a surface of one of the electronic components to corresponding pads on the surface of the other component. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multi-layer ceramic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10×10 array on the multi-layer ceramic surface.
In
FIG. 1
, a typical electronic module
100
comprises a semiconductor chip
11
, a substrate
13
and solder joints
15
. The solder joints
15
may be lead/tin, or some other alloy, and may be fabricated by several technologies including evaporation or electroplating. The solder joints
15
can be formed by depositing solder bumps on the chip
11
forming metal receiving pads (not shown) on the substrate
13
which correspond to the solder joints
15
on the chip
11
. Connection occurs when the chip
11
is aligned to the substrate
13
, and the assembly is exposed to temperatures higher than the melting point of the solder. This so-called reflow and chip-join results in the fully assembled module
100
, in which the circuits of the chip
11
are interconnected to the substrate
13
. The substrate is then capable of providing power, along with input and output signals, to and from the chip.
During normal operation, the entire module is subject to temperature excursions due to the functioning of the circuits on the chip, resistance heating of the solder joints, the wiring within the chip, and the wiring within the substrate. This heating results in the expansion and contraction of all of these components as temperatures rise and fall. Chips are primarily comprised of silicon, which has a coefficient of thermal expansion in the range of about 3.0 ppm/° C. The corresponding substrates to which the chips are joined are typically made of ceramic or organic materials, which have coefficients of thermal expansion in the ranges of about 5 to 7 ppm/° C. and about 12 to 20 ppm/° C., respectively. As a result, the chip and the substrate expand and contract at different rates during thermal cycling. This mismatch places stresses on the solder joints, and over time results in the fatigue of the solder joints. Eventually, continual stressing causes cracks to propagate completely across the solder joints leading to electrical failure of the electronic module.
Useful product designs dictate that the fatigue life (time until failure) of solder joints in a flip-chip module be significantly greater than the reasonable expected life of the component. There is much prior art which addresses how to increase the longevity of flip-chip modules. For example, both empirical and modeling data exist which optimize the pad sizes on both the chip and the substrate, along with the solder volume, in order to minimize stresses induced by thermal extremes. In addition, the spatial configuration or layout of the interconnects can be manipulated to provide minimum thermal fatigue exposure. However, in many cases, this type of optimization is not sufficient to achieve a useful product life.
A prior art method of redistributing the stresses on the solder joints has been to underfill the space between the chip and the substrate with an underfill material as shown in FIG.
2
.
FIG. 2
depicts electronic module
200
having a chip
11
joined to a substrate
13
connected together by solder joints
15
. A liquid underfill
17
, such as a filled epoxy resin, is disposed between the chip
11
and the substrate
13
to fill the space between the chip and substrate. The underfill
17
is typically chosen to have a coefficient of thermal expansion approximately equal to the solder upon curing. The underfill
17
serves to distribute the stresses that would otherwise be concentrated on localized regions of the solder joints
15
. The solder joints
15
become more immobilized such that they can tolerate repeated thermal cycling, to the extent that product requirements can be satisfied.
Although a proven means by which to enhance flip-chip reliability, underfill processes are often extremely difficult and expensive to execute. They are quite sensitive to the material flow properties of the liquid resin, and their success is highly dependent upon module geometry. Modules built with larger chips and very densely populated arrays are more difficult to underfill than those built with smaller chips. Problems with adhesion and voiding are common, and difficult to control. In addition, this type of processing is not easily extended to smaller dimensions: e.g., chip-to-substrate spacings of less than 2.5 mils, or to very large chips; e.g., greater than 20 mm on a side. Additionally, once the underfill is cured it is not easily removed, creating significant problems for chip removal and replacement.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus which facilitates joining of a semiconductor chip to a substrate resulting in an electronic module less prone to mechanical and electrical failure.
It is another object of the present invention to provide an apparatus which facilitates the joining of a semiconductor chip to a substrate without the use of solder joints.
It is yet another object of the present invention to provide an apparatus which facilitates joining of a semiconductor chip having improved tolerances to the thermo-mechanical expansion and contraction of the chip and substrate during thermal cycling.
A further object of the invention is to provide a method of assembling electronic modules without the need for solder joints.
It is still yet another object of the present invention to provide a method of assembling electronic modules which maintain their integrity during thermal cycling.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The thermo-mechanical stress imparted to the solder joints is a function of the thermal cycling temperature extremes, differences in the coefficients of thermal expansion of the two interconnected materials, and the spacing between the two interconnected materials. This invention provides an easy and low cost method to vary the spacing. The thickness of the interposer can be chosen so as to provide the optimum spacing, balancing stress reduction and interposer manufacturability and interconnection. Conventional (prior art) solder bump interconnections with underfill cannot provide this spacing flexibility determination.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a flip chip semic

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