Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-07-17
2007-07-17
Smith, Zandra V. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S736000, C438S738000, C438S743000, C438S744000
Reexamination Certificate
active
11161067
ABSTRACT:
Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.
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Li Ying
Tessier Brian L.
Zhong Huicai
Zhu Huilong
Advanced Micro Devices , Inc.
C. Li Todd M.
Hoffman Warnick & D'Alessandro LLC
Smith Zandra V.
Thomas Toniae M.
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