Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-01-06
2001-06-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S541000, C438S653000
Reexamination Certificate
active
06251800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to an ultrathin deposited gate dielectric formed using in-situ deposition and anneal processes.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide (“oxide”), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 1.0 &mgr;m critical dimension. As feature size decreases, the sizes of the resulting transistor and the interconnect between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
Another factor driving reduction of gate oxide thickness is the increased transistor drain current realized for a reduced gate dielectric thickness. Higher transistor drain currents are desirable because they allow each transistor to drive a greater number of other transistors, and can result in increased switching speeds. The transistor drain current is proportional to the amount of charge induced in the transistor channel region by the voltage applied to the gate conductor. The amount of charge induced by a given voltage drop across the gate oxide is the voltage drop multiplied by the capacitance of the oxide. Increasing the capacitance of the oxide therefore increases the transistor drain current. The capacitance C of the oxide can be written as for a parallel plate capacitor:
C=&egr;A/t
ox
,
where &egr; is the permittivity of the oxide, A is its area, and t
ox
is the oxide thickness. It can be seen that reducing oxide thickness increases the oxide capacitance and thereby the drive current of a transistor.
A gate oxide is typically grown onto the upper surface of a silicon substrate by heating the substrate to a temperature greater than about 700° C. in an oxidizing ambient. Such thermal oxides have been traditionally preferred over deposited oxides because thermal oxides generally exhibit lower trap state densities within the oxide and at the silicon/oxide interface. Trap states are energy levels, typically associated with impurities or defects, that can trap electrons or holes at the location of the impurity or defect. “Hot” carriers, or carriers which attain high kinetic energy (typically from the electric field moving them along a transistor channel), are particularly susceptible to being injected into the oxide and captured by trap states there. If a sufficiently high density of trap states is associated with an oxide, charge may build up in the oxide as carriers become trapped. This can lead to shifts in the transistor threshold voltage with time.
Although thermal oxides are attractive because of the low trap densities associated with them, growth of very thin thermal oxides (less than about 100 angstroms thick) does present difficulties. For example, the growth rate of a thermal oxide is dependent on oxide thickness for a given set of growth conditions. In particular, the growth rate is more rapid during the initial stages of growth than it is after growth of approximately 300 angstroms of oxide. Initial-stage oxide growth can be modeled using a growth rate which decreases exponentially with increasing thickness. This strong variation of growth rate for low oxide thicknesses makes it difficult to grow controllable, reproducible oxides with thicknesses of less than about 50 angstroms. Another problem with growing very thin oxides is that roughness, contamination, and imperfections in the starting silicon surface become increasingly important to the integrity of the grown oxide. Any locally weak or excessively thin spots may become preferred sites for breakdown of the oxide when exposed to electric fields during device operation. Breakdown is a potential problem with very thin oxides, whether they are grown or deposited, and may be precipitated by physical defects such as pinholes or thin areas. Trap states within the oxide may also lead to breakdown, by trapping charge which causes locally elevated electric fields. Tunneling current through the oxide may be locally increased as a result of such an elevated field, leading to breakdown.
It would therefore be desirable to develop a method for controllable, reproducible formation of ultrathin (less than about 50 angstroms thick) gate oxides. The desired gate oxide should be breakdown-resistant and substantially free of trap states which may cause V
T
shifts.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by a low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) process for oxide deposition, and the resulting ultrathin, reproducible gate oxide. The gate oxide may be used in semiconductor devices including, for example, transistors and dual-gate memory cells. Furthermore, this deposited gate oxide may be used alone or as part of a stacked oxide combining thermal and deposited portions. The oxide is grown by PECVD using silane and nitrous oxide (N
2
O) sources and a lowered chamber pressure, as compared to conventional PECVD oxide depositions, of approximately 1.1 to 1.3 torr. A comparatively low radio frequency (RF) power density of less than about 0.15 W/cm
2
is also used. These low-power, low-pressure conditions allow for extremely rapid stabilization of plasma conditions, such that deposition may be performed in increments at least as short as 0.1 second. For each 0.1 second deposition increment, an oxide thickness of between about 1 angstrom and about 2 angstroms is deposited. In this manner, extremely thin oxides can be deposited controllably and reproducibly. In contrast to thermal growth of thin oxides, the deposition rate of the low-power, low-pressure PECVD oxide is substantially constant. The deposition temperature is preferably between about 390 and about 410° C.
In a preferred embodiment, the oxide is grown in a deposition chamber associated with a “cluster tool” such as those commonly used in the semiconductor industry. Cluster tools include chambers grouped together so that multiple deposition, etching, or other processes can be performed sequentially without exposing substrates to room air in the interim between processes. The CVD chambers often have multiple (for example, six) substrate mounting positions. A substrate is moved sequentially into different positions during a deposition such that a portion of the deposition takes place with the substrate in each of the mounting positions in the chamber. For example, a substrate may be loaded into the first
Gardner Mark I.
May Charles E.
Sun Sey-Ping
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Dang Phuc T.
Nelms David
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