Ultrasonic spray coating of liquid precursor for low K...

Details Ultrasonic spray coating of liquid precursor for low K... Ultrasonic spray coating of liquid precursor for low K...

2000-10-18

2003-06-24

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S761000, C438S778000, C438S782000, C427S240000, C427S372200, C427S452000

Reexamination Certificate

active

06583071

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the formation of dielectric layers. More particularly, the present invention relates to a method for forming a low dielectric constant film that is particularly useful as a premetal or intermetal dielectric layer in an integrated circuit.
Semiconductor device geometries have dramatically decreased in size since integrated circuits were first introduced several decades ago, and all indications are that this trend will continue on. Today's wafer fabrication plants are routinely producing devices having 0.25 &mgr;m and even 0.18 &mgr;m feature sizes, and the plants of the future will soon be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, one issue that has become an increasing concern to semiconductor manufacturers is that of interlevel “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to isolate them from each other.
Another issue that is becoming more of a concern with decreasing feature sizes is the “RC time constant” of a particular trace. Each trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
Hence, in order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators having a low dielectric constant. And as mentioned above, low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption.
The traditional insulator used in the fabrication of semiconductor devices has been undoped silicon oxide. Undoped silicon oxide films deposited using conventional CVD techniques may have a dielectric constant (k) as low as approximately 4.0 or 4.2. Many approaches have been proposed for obtaining insulating layers having a lower dielectric constant. Amongst these have been fluorine-doped silicon oxide films (FSG films) that may have a dielectric constant as low as about 3.4 or 3.6.
Several semiconductor manufacturers, materials suppliers and research organizations have focused on identifying and developing dielectric films having a dielectric constant below that of FSG films. These efforts have resulted in the development of low and extremely low dielectric constant films. As used herein, low dielectric constant films are those having a dielectric constant between 3.0 to 2.5 and extremely low dielectric constant (“ELK”) films are those having a dielectric constant below 2.5 extending to dielectric constants below 2.0.
Some approaches to developing such low K and ELK films include introducing porosity into known dielectric materials to reduce the material's dielectric constant. Dielectric films when made porous, tend to have lower dielectric constants (the dielectric constant of air is normally 1.0). One method of forming porous oxide films is referred to as the sol gel process, in which high porosity films are produced by hydrolysis and polycondensation of a metal oxide. The sol gel process is a versatile solution process for making ceramic material. In general, the sol gel process involves the transition of a system from a liquid “sol” (mostly colloidal) into a solid “gel” phase. The starting materials used in the preparation of the “sol” are usually inorganic metal salts or metal organic compounds such as metal alkoxides. The precursor solutions are typically deposited on a substrate by spin on methods. In a typical sol gel process, the precursor is subjected to a series of hydrolysis and polymerization reactions to form a colloidal suspension, or a “sol.” Further processing of the “sol” enables one to make ceramic materials in different forms.
In one particular sol gel process for forming a porous low dielectric constant film, surfactants act as the template for the film's porosity. The porous film is generally formed by the deposition on a substrate of a sol gel precursor followed by selective evaporation of components of the sol gel precursor to form supramolecular assemblies. The assemblies are then formed into ordered porous films by the pyrolysis of the supramolecular templates at approximately 400° C. However, for this process the pyrolysis step can require as much as four hours to extract the surfactant and thus leave behind a porous silicon oxide film. Such lengths of time are incompatible with the increasing demand for higher processing speeds in modem semiconductor processing.
FIG. 1
is a flowchart illustrating a basic sol gel process that has been previously proposed to deposit low k dielectric films. As shown in
FIG. 1
, the first step is the synthesis of the stock precursor solution (step
100
). The stock precursor solution is prepared by mixing a soluble silicon oxide source, e.g., TEOS (tetraethoxysilane), water, a solvent, e.g. alcohol, and a catalyst, e.g. hydrochloric acid, at certain prescribed environmental conditions and refluxed for certain time periods at particular mole ratios.
Once the stock solution is obtained, the coating solution is mixed (step
110
). The general procedure to prepare the coating solution is to add to the stock solution a surfactant, more TEOS, more water, more solvent, and more catalyst. Surfactants are used as templates for the porous silica. In later processes the surfactants are baked out, leaving behind a porous silicon oxide film. Typical surfactants exhibit an amphiphilic nature, meaning that they can be both hydrophilic and hydrophobic at the same time. Amphiphilic surfactants posses a hydrophilic head group or groups which has a strong affinity for water and a long hydrophobic tail which repels water. The long hydrophobic tail acts as the template which later provides the pores for the porous film. Amphophiles can aggregate into supramolecular arrays which is precisely the desired structure that needs to be formed as the template for the porous film. Templating oxides around these arrays leads to materials that exhibit precisely defined pore sizes and shapes. The surfactants can be anionic, cationic, or nonionic. The acid catalyst is added to accelerate the condensation reaction of the silica around the supramolecular aggregates.
After the coating solution is mixed it is filtered and deposited on the substrate (step
120
) using a spinning process where centrifugal draining ensures that the substrate is adequately coated with the coating solution. The coating solution is then applied onto the surface of the substrate to be coated

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