Ultra-thin SOI MOSFET method and structure

Details Ultra-thin SOI MOSFET method and structure Ultra-thin SOI MOSFET method and structure

2006-06-13

2006-06-13

Luu, Chuong Anh (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S655000, C438S682000, C438S592000

Reexamination Certificate

active

07060546

ABSTRACT:
An ultra-thin, scaleable MOSFET transistor and fabrication method are described. The transistor features fully self-aligned, raised source/drain junctions on a thin SOI wafer and exhibits low contact resistance, low gate resistance and good device isolation characteristic. No extra lithographic mask steps are required beyond those required by conventional processes. The transistor is completely “bracketed” or surrounded by STI (shallow trench isolation), providing inherent isolation between it and any other devices on the SOI wafer. Gate sidewall spacers are formed outside of the gate area so that the scalability is limited solely by lithography resolution.

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